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Flip-Flops Computer Organization I 1 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high duration; the low duration is defined similarly. The cycle time of a clock is the sum of its high duration and its low duration. The frequency of the clock is the reciprocal of the cycle time. Clocks high low time rising edge falling edge
Flip-Flops Computer Organization I 2 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens State Elements A state element is a circuit component that is capable of storing a value. At the moment, we are interested primarily in state elements that store logical state information about the system, rather than data storage. A state element may be either unclocked or clocked. Clocked state elements are used in synchronous logic -When should an element that contains state be updated? -Edge-triggered clocking means that the state changes either on the rising or the falling edge. -Clock edge acts as a sampling signal that triggers the update of a state element. A signal that is to be written into a state element must be stable; i.e., it must be unchanging. If a function is to be computed in one clock cycle, then the clock period must be long enough to allow all the relevant signals to become stable.
Flip-Flops Computer Organization I 3 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens Set-reset Latch NOR gate output is only 1 when both inputs are 0 Feedback: output depends both on present inputs and past inputs If the output of one NOR gate is 1 then the output of the other must be 0 A latch is a circuit that has two stable states, and so can store 1 bit of data. Common contemporary terminology is that a latch does not receive a clock signal, and hence is transparent. However, usage does vary…
Flip-Flops Computer Organization I 4 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens Set-reset Latch … then Q == 1 Toggle the Set input to 1… Then, toggle the Set input to 0… … and Q == 1 So, toggling S on causes the latch to store 1; subsequently, toggling S does not change the state of the circuit.
Flip-Flops Computer Organization I 5 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens Set-reset Latch … then Q == 0 Toggle the Reset input to 1… Then, toggle the Reset input to 0… … and Q == 0 So, toggling R on causes the latch to store 0; subsequently, toggling R does not change the state of the circuit.
Flip-Flops Computer Organization I 6 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens Set-reset Latch … then both NOR gates would emit values of 0, breaking the Q/~Q relationship… … and there are instability issues in actual hardware implementations Setting both inputs to 1 simultaneously is not allowed… Setting both inputs to 0 simultaneously results in a "keep" state… … the latch will maintain its current value indefinitely (logically)
Flip-Flops Computer Organization I 7 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens The gated D-latch can be derived from the set-reset latch by adding an interface that makes it possible to essentially isolate the set-reset logic: Gated D-latch If the Enable input is 1 then the value of D will immediately be stored by the S-R mechanism. If the Enable input is 0 then the value of the S-R mechanism is fixed. The S = R = 1 case cannot occur for the embedded S-R latch, because…
Flip-Flops Computer Organization I 8 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens There is a small, but positive delay between changes in the input values to a logic gate and any resulting change in the gate's output. We call this the gate delay. Consider the following circuit: Timing Issues Logically, the output of the circuit should ALWAYS be 0. Why? Consider what happens if the input signal A is set to 1: - A0, A1 and A2 immediately become 1 -after one gate delay, the output X will become 1 since the XOR has inputs of 0 and 1 -at the same time, the output of the AND gate will become 1 -after one more gate delay, the output X will become 0 again What would happen if the output X were used as input to another circuit? We can prevent that if we use a clock signal to synchronize operations.
Flip-Flops Computer Organization I 9 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens We create a clocked D-latch by connecting the Enable input of the gated D-latch to a clock signal: Clocked D-latch The clocked D-latch accepts the input D only when the clock signal is high (1). However, there is still a hazard… what if the value of D can change more than once during the high-duration of the clock signal? The clocked D-latch is level-triggered… that is, whether its state can change depends on the level of the clock signal.
Flip-Flops Computer Organization I 10 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens Clocked D Flip-flop Consider what happens when we combine a clocked D-latch and a clocked S-R latch: clocked D-latchclocked S-R latch inverted clock The output of the device can only change once per clock cycle… shortly after the clock signal goes low. 2 gate delays D
Flip-Flops Computer Organization I 11 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens Clocked D Flip-flop Suppose that D is set to 1; nothing happens at all until the clock signal also goes high: clocked D-latchclocked S-R latch inverted clock The output of the D-latch goes high (i.e., takes the value of D ) but only after two gate delays. By then, the S-R latch is seeing a low clock signal, and so the S-R latch does not change state yet. 2 gate delays D
Flip-Flops Computer Organization I 12 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens Clocked D Flip-flop Then, when the clock goes low… clocked D-latchclocked S-R latch inverted clock The S-R latch sees a high clock signal (after 1 gate delay), and so it updates state. But, the D-latch sees a low clock signal immediately and so it cannot change state. 2 gate delays D
Flip-Flops Computer Organization I 13 CS@VT June 2010 ©2006-10 McQuain, Feng & Ribbens JK Flip-flop The JK flip-flop takes two data inputs and updates its state Q, on a clock tick, according to the table: J K Q ~Q CK J K Q ~Q ---------------------- 0 0 no change 0 1 1 0 1 1 opposite Commonly, it takes an entire clock cycle for the JK flip-flop to update its state, and so the change in state is commonly seen on the falling edge of the clock cycle. It is also common to provide additional input connections for clear and reset and enable signals.
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