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Effective RTL coding rules to avoid Simulation Shoot-thru Udit Kumar 1, Bhanu Prakash 1, Olivier Florent 1, Paras Mal Jain 2, Anshu Malani 2, Shaker Sarwary.

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Presentation on theme: "Effective RTL coding rules to avoid Simulation Shoot-thru Udit Kumar 1, Bhanu Prakash 1, Olivier Florent 1, Paras Mal Jain 2, Anshu Malani 2, Shaker Sarwary."— Presentation transcript:

1 Effective RTL coding rules to avoid Simulation Shoot-thru Udit Kumar 1, Bhanu Prakash 1, Olivier Florent 1, Paras Mal Jain 2, Anshu Malani 2, Shaker Sarwary 2 1 STMicroelectronics 2 Atrenta Inc.

2 Name, Affiliation and Author NameAffiliation Udit Bhanu Olivier Paras Mal JainAtrenta Anshu MalaniAtrenta Shaker SarwaryAtrenta

3 Abstract RTL simulations do not consider timing in all aspects and therefore, the results produced by simulation may differ from silicon behavior. Simulation can miss design bugs due to limitations in simulator. These differences are due to incorrect estimation of propagation time between clock and data paths causing data to propagate earlier than in silicon. This problem is known as shoot-thru. We faced a silicon failure which prompted us to understand how shoot-thru situations occur during simulation, identify these situations with higher accuracy of analysis and fix them with minimal impact using simple RTL coding rules. We teamed up with Atrenta to automate efficiently the check of those coding rules.

4 What is Shoot-thru? When any signal jumps over an extra register within one clock cycle.  E.g. Input “din” crosses 2 register within one clock cycle. 4 In silicon => gate delay In simulator => events Shoot-thru: (events in data path ) <= (events in clock path) Shoot-thru: (events in data path ) <= (events in clock path) clk dint din dout cint D D

5 How Simulation Shoot-thru occurs? 5 dint din dout clkcint D D dint 0>1 cint 0>1 dout 0>1 Consequence : “dout” same as “din” within single clock clk 0>1 Reason : Extra Delta delay in Clock Path clk cint din dint dout

6 Will Verilog coding rules help? 6 // Input data sampling (posedge clk, negedge rst_n) begin if (rst_n==1’b0) dint <= din; else dint <= din; end // Capture data on divided clock (posedge cint, negedge rst_n) begin if (rst_n==1’b0) dout <= 1’b0; else dout <= dint; end // Sequentioal clock generation (posedge clk, negedge rst_n) begin if (rst_n==1’b0) cint <= 1’b0; else cint <= !cint; end blocking assignment in combination blocks and non-blocking in sequential  Not, always safe…. dout clkcint din dint D D cdiv Non-blocking assignments consume delta delay Extra Delta-delay in Clock Path

7 Case 1: Verification can miss Shoot-thru 7 User specification was to transfer “din” to “dout” in 1 cycle Extra flop was a mistake but not caught by RTL verification. din dout clk cint dint D D Silicon fails as “din” will be captured at “dout” in 2 cycles => one cycle extra delay vs. Specification If Simulation has shoot-thru => “din” will be captured at “dout” in 1 cycle => All tests pass as per user specification Existence of One extra flop causes silicon failure.

8 Case 2: Verification can miss Shoot-thru 8 User specification was to transfer “din” to “dout” in 2 cycle However, shoot-thru may cause simulation failure User fixes it by adding an extra flop Simulation Fails din dout clk D D Silicon Fails din dout clk D D D Simulation Passes after rtl changes din dout clk D D D New Flop

9 Potential Gap in design flow Verification Gate Level Simulation can detect shoot-thru N/l Simulation Pros: Verification at gate level represents Silicon. Cons: Huge data base and run time. Pros: Verification at gate level represents Silicon. Cons: Huge data base and run time. Functional Design Verification Synthesis Physical design HDL Gates Silicon Functional Specification Equivalence check

10 By using an improved simulator?  NO, as root cause of problem is that RTL Simulation has no notion of timing delay & Hold checks. 10 By doing Gate level simulation?  Yes but it is very costly. By using robust RTL coding rules?  Yes! this is easy and efficient (see subsequent slides) So, How to detect shoot-thru issues?

11 Rule 1 - Force scheduling of data 11 din dout clkcint dint D D This adds an extra delay in data path dint<= din after 1 ns; VHDL dint <= #1 din ; Verilog Force physical time delay in Sequential data assignments Signal is delayed in ‘physical time’, instead of ‘delta’ time.

12 Rule 2 - No ‘physical delay’ in clock path Delay on clock paths competes with delay on Data path Clock vs Data scheduling still un-reliable 12 din dout clkcint dint D D Rule1 + Rule2 ensures no risk of shoot-thru i.e data is updated after clock after 1ns No unwanted delay on clock path

13 Automation with SpyGlass RTL checker 13 din dout clkcint D D If delta delay is different between launch and capture flop, add delay on launch flop Rule 1 – Reports missing needed delay in data path Rule 2 – Reports extra delay (Physical) present in clock path din dout clkcint dint D D Easy to identify shoot-thru prone RTL

14 Checker catches Real Silicon Issues 14 din dout tck D D logic Missing delay at source din dout tck D D clkD Extra delay in clock divider Missing delay was causing silicon failure Unintentional delay in clock path found on another chip  User specified physical delay on source flop - Still problem occurred due to physical delay specified on clock path Buffer, Clock gating etc.

15 Conclusion Simulators create events and schedule them, but with no notion of timing checks across data and clock events Shoot-thru impacts RTL Simulation and may cause false simulation behavior, masking the real issues Simple RTL coding rules can prevent the problem to occur  Possibly add physical delays on data path to force scheduling  Avoid physical delays on clock path Spyglass RTL checker can help you to efficiently check those rules and removes need of costly gate level simulations. Next Steps  Extend the SpyGlass checks to ensure that every output interface is having delayed assignment 15


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