Presentation on theme: "RoD set-up for the TileCal testbeam, 2003 period. 9th Workshop on Electronics for LHC Experiments Amsterdam, 30 september 2003 Jose Catelo, Cristóbal Cuenca,"— Presentation transcript:
RoD set-up for the TileCal testbeam, 2003 period. 9th Workshop on Electronics for LHC Experiments Amsterdam, 30 september 2003 Jose Catelo, Cristóbal Cuenca, Esteban Fullana, Emilio Higón, Belén Salvachúa, José Torres Universitat de València
RODdemo installation Motivation: first time we install a readout system with complete I/O optical fibre and DSP processing capabilities implementing online algorithms like Optimal Filtering in a testbeam environment. Objectives: Gaining expertise in a closer-to-ATLAS environment. Testing the RODdemo in with input/output S-Link. Processing real data with several online algorithms (Optimal Filtering and Flat Filtering) Not disturbing the actual ROD Emulator (i.e. parallel working)
Parallel readout No interferences with working RODEmulator data acquisition Test the dual fiber readout of the interface link Interface Link FEB Electronics (DRAWER) 8 DIGITIZERS (48ch: 2 TileDMU/3ADC each) Data TTC Optical Splitter LC conn. Testbeam’s ROD emulator + ROS RODdemo + Data acquisition workstation Testbeam TTC system DISTRIBUTION
CT SBC (VP110) P2 P1 P3 RoD Crate (9U) PCI Bus ROD control+DAQ ROB (linux_PC) S32PCI64 ODIN LDC FEB Electronics (DRAWER) Integrated ODIN LSC TM4Plus1 PU DSP6202 @250MHz ROD Demo Integrated ODIN core Int. Link Pattern generator or Digitizer data FIFO+Data management DSP OF. Algo. Input FPGA DATA and TTC FIFO RODLib + Online root_ctrl RCC DHCP kernel+NFSSimple Data Dump App Interface Link RCC ODIN LDC TTCpr NetWork Testbeam TTC system Input FPGA DATA and TTC FIFO RODLib + Online root_ctrl Integrated ODIN core
RODdemo testbeam status TTC: TTCpr software application using dataflow and vme_rcc drivers and sending the TTC info to VME slave module (RODdemo). OK! Dataflow: I/O slink transition module TM4Plus1: Data input firmware OK! Data output firmware: problem with integrated ODIN LSC. Manually fitted into APEX fpga. OK! DSP Processing Unit: DSP: New DSP online algorithm developed in “C” for testebam set-up. OK! Input FPGA firmware: Solved initial problems. Now is implemented the TTC FIFOS and data storage in Dual Port Memory. OK! ROB emulator workstation: Simple program for dumping the acquired data is done. OK! Control and monitoring: Standalone applications running in RCC with Dataflow and RODlib libraries. This application also polls PCI bus (ttcpr) for getting TTC info and sending it to VME ROD module. OK!
Online Algorithms implementation Implemented 2 online algorithms for offline validation: OF and FF.
Preliminary results. Analyzing binary dumps with ROOT (Ttrees) Energy reconstruction for PMT 16 of B+ All of them in ADC counts. Optimal Filtering Energy Reconstruction OF Offline OF DSP OF (DSP-Offline)
Energy reconstruction for PMT 16 of B+ All of them in ADC counts. Pedestal no subtracted. Flat Filtering Energy Reconstruction FF Offline FF DSP FF (DSP-Offline) Preliminary results. Analyzing binary dumps with ROOT (Ttrees)
The data acquisition system requirements: Input Links (main constraint): 12 drawers Processing power: not essential Trigger rate: ~ 1 to 100Hz. Trigger system hardware: Optical: from TTCvx/ex to a TTCpr FEB trigger: The trigger could be recover from data at arrival, because the S-Link recovers a data triggered when a header 0x51115110 control word and CAV line is asserted. The Hardware availability for the test dates could define which ROD set-up to be used (all need a 9U crate): 2 final ROD motherboards without PUs 2 final ROD motherboards with 2 PUs each
Diagram & HW needs with final ROD motherboard without PUs The trigger should be recovered from data or VME trigger with TTCpr mounted on a SBC (rod controller). The DAQ computer could be a SBC CT-VP110 that configures the crate and could readout the motherboard with VME bus at lower rates We need to program staging FPGA for send data directly to VME FPGA and finally to SBC. There is a low speed data path available for this and enough for cosmic ray set-up data rates. Hardware needs: 2 ROD motherboards : available between half and end of October. For the new board we change some tips in schematics for trying to solve the initial g-link clock lock problem seen in initial prototypes at university of Geneva for 40Mhz clock. 1 SBC: The recommendation is to use the ATLAS standard SBC from concurrent technologies. The Valencia group has one available, configured for network booting and tested in lab and at testbeam with a TTCpr card mounted. 12 multimode standard fibers. The g-link inputs of rodmotherboards are ST type as the drawers, so no adapter is needed.
Diagram & HW needs with ROD motherboard with PUs The trigger and DAQ would be implemented with TTCpr and SBC CT-VP110 as well as in the previous configuration. With the Pus, we can test them on final ROD and implement some algorithm in DSP if needed. Hardware needs: 2 ROD motherboards 4 Processing Units: we expect to receive them for the beginning of November. (Input FPGA and new DSP require programming from scratch) 1 SBC 12 multimode standard fibers ST-ST
Conclusions The goal was reached. We close the readout chain between the drawer and the ROB with I/O optical links and DSP processing. We need to complete the preliminary analysis from physics data acquired. (results on http://ific.uv.es/tical/rod/ROD_Pages/data_f/rod_data_format.html) Commissioning will give us an essential expertice with ATLAS-like configuration.