1. Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex Circuits Fabian Vargas, Alexandre Amory vargas@computer.org Catholic University – PUCRS Electrical Engineering Dept. Av. Ipiranga, 6681 90619-900 Porto Alegre Brazil

2. vargas@computer.org2 Summary 1. Motivation and Preliminary Considerations 2. Circuit Modeling and Fault Injection Approach 2.1. VHDL Skeleton and the Error Management Unit 3. Development of the Statistical Models 3.1. SEU Rate –Cross-Section –Error (SEU) Rate 3.2. MTTF Rate –Reliability Model 4. Discussions & Example of Computation 4.1. 3 FT-implementations: Data-path, Control-path, Both 5. Final Considerations

3. vargas@computer.org3  In 1962: first predictions of existence of such a phenomena.  By the year of 1975: existence of Single-Event Upsets (SEUs) was verified in practice.  From that time to now: - Extensive theoretical work to explain failure mechanisms, - Sophisticated test techniques and procedures developed to extrapolate the laboratory data failure rates to realistic radiation environments like space, nuclear power plants, or commercial flights (33,000 feet). 1. Motivation and Preliminary Considerations

4. vargas@computer.org4  Laboratory experiments are typically performed using the in-flux test method: high-energy particle accelerator (cyclotron).  In practice, only one type of ion specie is used (associated high-cost to change ion sources into the accelerator).  The DUT package lid is removed and placed in a vacuum chamber. The test socket is mounted on a platform which can be rotated so that the angle of incidence between the ion beam and chip surface can be changed.  The DUT is electrically exercised by a tester connected to the test socket through a set of cables and special connectors to the vacuum chamber. 1. Motivation and Preliminary Considerations

5. vargas@computer.org5 In summary, the In-flux Test Method...  Provides very accurate SEU rate predictions.  Drawbacks: - high cost associated: two or three cyclotron hours may result in some thousands of tenths of dollars. - requires the development of specific HW (and SW) interfaces: which takes money and time during the design process. - “time-to-market” is affected: development of rigorous test sets, which take long procedures to be validated before the device characterization step itself takes place. 1. Motivation and Preliminary Considerations

6. vargas@computer.org6 Compared to traditional in-flux test methods:  does not require laboratory experiments to characterize microelectronic devices for operation in radiation environments  execution simplicity  intrinsic low-cost  presents not only fault injection mechanisms adapted to circuits modeled in VHDL, but it also considers a fault modeling strategy that represents real radiation-induced transient faults (SEUs) in memory elements. 1. Motivation and Preliminary Considerations

7. vargas@computer.org7 Fig. 1. Comparison between the design flows of devices for operation in radiation environments: (a) the traditional in-flux method and (b) the proposed approach. (a) (b) 1. Motivation and Preliminary Considerations

8. vargas@computer.org8 2. Circuit Modeling & Fault Injection Approach 1) Generate and instantiate an “Error Management Unit - EMU” inside the architecture of the circuit VHDL main code. F Goal  control the fault injection process during fault simulation 2) Run Srand Algorithm from the C-ANSI language: F Goal  random generation of the time instants to inject faults during simulation. Goal  prepare the VHDL code to run in a fault simulation process.

9. vargas@computer.org9 Inside the EMU architecture, two Linear Feedback Shift Register (LFSR) entities: LFSR_Reg_ Selector and LFSR_Bit_ Selector are instantiated as Components : a) LFSR_Reg_ Selector  selects the memory element to which the transient fault will be injected. b) LFSR_Bit_Selector  selects the bit position in the memory element that will be upset.  Note: these LFSRs are implemented by modified primitive polynomials in order to generate all 2 n memory element addresses and 2 m bit positions. 2. Circuit Modeling & Fault Injection Approach

10. vargas@computer.org10 Functions of the Error Management Unit - EMU: n a) reads data from external file: randtime.txt to determine the: F time instants to inject faults F initial seeds for the LFSR processes n b) generates a simulation report file: result.txt, which contains information about: F the total # of faults injected, F the list of memory elements and bit positions affected by faults, F the # of faults injected in each one of these elements. 2. Circuit Modeling & Fault Injection Approach

11. vargas@computer.org11 Fig. 2. VHDL skeleton generated by the “circuit modeling & fault injection” strategy. This skeleton-based VHDL code is melt to run in a fault simulation set. Main characteristic: the ease automation of the procedure by which the skeleton can be generated from a synthesizable VHDL circuit description.

12. vargas@computer.org12  L = N, given in [(errors.device)/(particles.bit)]  1 R where: N: # of functional errors [errors].  1 : total # of faults injected during fault simulation [faults/device]. R: # of memory cells [bits]. =  L  2, given in [errors/(bit.s)] where:  L : cross section of the CUT [(errors.device)/(faults.bit)].  2 : frequency of which faults are injected in the circuit in real environment [faults/device.second]. SEU Rate : Cross Section : 3. Development of the Statistical Models 3.1. SEU Rate

13. vargas@computer.org13 P 1,1 = 1 - e -  t (I) P r,n = C n,r.P 1,1 r.(1 - P 1,1 ) n - r (II) R 1 (  t) = 1 - P r,n r = d + 1 (III) R 1 (N  t) = [1 - P r,n ] N (IV) R w (N  t) = [1 - P r,n ] NW (V) MTTF =  0  R w dt (VI) R w (N  t) = {[1 - P r,n ] Wt/  t } t (VII) MTTF = -  t (VIII) W.ln[1 - P r,n ] MTTF1 = -  t (IX) W 1.ln[1 - P r,n1 ] MTTF CC = MTTF MIN (MTTF 1, MTTF 2,..., MTTF n ) (X) 3. Development of the Statistical Models 3.2. MTTF Rate

14. vargas@computer.org14 Table 1.General characteristics of the Microprocessor R3: a primary case-study for the proposed methodology. 4. Discussions and Example Computation

15. vargas@computer.org15  We generated 3 different fault-tolerant (FT) implementations of the R3 processor.  Based on the use of information redundancy (Hamming Code + 1 Parity Bit per register) to protect the memory elements: a) only in the datapath (version 1); b) only in the control path (version 2); c) in both parts of the processor (version 3). 4. Discussions and Example Computation

16. vargas@computer.org16  Case Study...  Commercial aircraft flying at 33,000 feet altitude during a time period of 10 hours.  According to [10], at this region, high-energy particles are represented mainly by neutrons, whose energy varies up to 100MeV, in a flux up to 10 particles/(cm2.hour). (  Note: this energy is large enough to produce an upset at circuits designed with the present state-of-the-art submicronic technologies).  We assumed the “worst case” parameter: 10 particles incident on the circuit, with all of them producing an upset per hour of circuit operation.  We developed an application program that was run in the 3 different FT versions of the processor, one at a time.  Srand Program generated a total # of 239 time instants for a pre-specified VHDL code fault simulation time of 4 hours. 4. Discussions and Example Computation

17. vargas@computer.org17 Table 2.Fault simulation summary for the 3 FT versions of the R3 processor described in VHDL 4. Discussions and Example Computation

18. vargas@computer.org18  We presented a novel approach based on a VHDL description to predict the SEU rate and the mean time to failure (MTTF) for complex circuits.  Compared to traditional in-flux test methods: does not require laboratory experiments. due to its simplicity, it presents an intrinsic low-cost. presents not only fault injection mechanisms adapted to circuits modeled in VHDL, but it also considers a fault modeling strategy that represents real radiation-induced transient faults (SEUs) in memory elements.  The methodology core: Error Management Unit - MEU, described in VHDL as an entity that is parameterized by the user.  Methodology automation: CAD tool to perform circuit modeling, fault injection and simulation data analysis.  EMU Program (emu.vhd): www.ee.pucrs.br/~vargas/Programs. 5. Final Considerations: