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Design and Layout Guidelines Robert Benjamin Applications Engineer

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1 Design and Layout Guidelines Robert Benjamin Applications Engineer

2 Information Sources

3 King Solomon: Book of Proverbs –15:22 Plans go wrong for lack of advice; many advisers bring success. –15:31 If you listen to constructive criticism you will be at home among the wise.

4 Information Sources Internet/Magazines (Printed Circuit Design and Fabrication) Trade Organizations (IPC, JEDEC, IEEE, SMTA) TI Internal Sites –http://pwrmkt.itg.ti.com/DesignTools.htmhttp://pwrmkt.itg.ti.com/DesignTools.htm Your Neighbor

5 Interference

6 RFI –Phones (Cell and Home) –Broadcast Stations –Wireless Technologies (Computers, Blu-Tooth, Tablets) EMI –Motors –Electrical Equipment –Power Sources (Man Made and Natural) ESD Crosstalk and Feedback

7 Circuit Issues

8 Key Circuit Issues Drift Linearity EMI/RFI Protection Component Selection

9 DC drift Every component is a potential drift source; but the reference usually out-drifts them all! Parasitic thermocouples can also cause drift – watch out!

10 In-circuit Thermocouples

11 DC linearity Consider driving differentially – also improves dynamic range Keep front-end balanced C0G caps if possible Keep reference impedance low

12 EMI/RFI Protection Inductors – Ferrites, Coils Capacitive Filters – Feed-Thru, X2Y Warning: Adding inductance to/through the ground connections will create more problems than it solves. Do NOT bridge Analog and Digital grounds with an inductor.

13 External ESD Protection A Need May Arise for Extra ESD Protection Schottky Diodes. Transient Voltage Suppression (TVS). ESD Protection Device ICs (TPD4E001.)

14 Moving from Circuit to Layout

15 Capacitor Selection Different Tasks Require Different Caps Bulk (Tantalum, MLCC) Bypass/Filter (MLCC-C0G, X2Y, X7R) Signal Path (Mica, PPS, Film, MLCC-C0G)

16 Signal Paths Require Quality Caps THD+N vs. Voltage for Various Capacitor Types

17 The X2Y Advantage Shorter current path, Smaller current loops Dual parallel current paths to ground reduce inductance Opposing current flow reduces mutual inductance by cancellation. The structure is balanced, resulting in exceptional common mode filtering. X2Y is typically 1/10th the inductance of a like-sized conventional MLCC. Unlike MLCCs, inductance does not increase with size.

18 PCB Layout Tips

19 Basic PCB Design Principles Separate Analog and Digital Signals Pay Close Attention on Connecting AGND and DGND Provide Good Ground Return Paths High Frequency Bypassing Minimize Inductance (Vital for HS) Control Thermocouples Fill void areas on signal layers with ground fill. Taking care of these things will also help improve EMI/RFI performance.

20 Traces

21 Board Traces Traces Can Act Like Antennas Traces Have Transmission Line Properties –Inductance –Resistance Traces for Power Should be Wide Connect and Terminate Effectively (vias)

22 Return Currents Analog Digital Source Signal Return Current

23 Loop Inductance

24 PCB Layout Tips High Resolution Measurements 1 inch (7 mil) trace of 1/2 oz copper with 10μA of current => voltage drop of 1.3μV 4 LSBs (298nV) at 24 bits! 1 inch 1.3µV 10µA

25 PCB Traces Resistive AND Inductive 1 inch 0.5 cm trace –Resistance = ohms –Inductance = 20 nH Current change of 100 mA in 30 nS –Resistive Voltage of 250 uV –Inductive Voltage of 70 mV

26 PCB Traces and Caps Example – Reference Circuit (REF50xx or Buffered by OPA350) –Schematic –Layout 1/(  (L * (C4*C5/(C4+C5))) 1/2 ) = 3.58MHz

27 PCB Layout Process Review the Schematic and Mark Sensitive Areas –Sensitive Analog Paths –EMI and Other Interference Sources –Heat Sources Consider External Connections Spend Considerable Effort In Planning (Part Placement and Desired Routing Paths) –Prioritize the Analog Portion –Power Routing and Planes –Bypass Caps and Other Critical Components –Different Packaging Alternatives

28 General Rules Parallel Components Can Electromagnetically Couple Traces Side to Side and Side by Side Can Couple Consider Thru-Hole Interaction Do Not Route Sensitive Nodes Through Components Surface Mount Has Less Inductance, But Remember the Path (Vias)

29 Component Rules Keep Analog Signal Paths Short Keep Inputs Away From Unwanted Outputs –Feedback –Oscillation Maintain Effective Ground Plane Keep Analog and Digital Portions Separate Power Entry Better Near the Outputs Keep Inputs and Outputs Separate –With Multiple Circuits Use Mirror Images –Planes and Shielding May Be Appropriate

30 Poor Bypassing Good Bypassing Bypass Capacitors DO NOT have vias between bypass caps and active device – Visualize the high frequency current flow !!! Ensure Bypass caps are on same layer as active component for best results. Route vias into the bypass caps and then into the active component. The more vias the better. The wider the traces the better. The closer the better. X2Y may be a better choice.

31 Starting the Layout Keep Analog I/O symmetrical Avoid putting heat sources near the Analog I/O Route Digital signals AWAY from the Analog signals Analog I/O

32 Split or Solid? Partition the board into Analog and Digital sections when the layout permits. Split the ground plane if needed – but don’t if you don’t have to! AnalogDigital

33 Digital Grounding Keeping ground traces short: –minimizes inductance –reduces voltage differential between the board and chip substrate –improves noise immunity Analog Ground Pin

34 Visualize Power Currents

35 Current Reference Design

36 The ADS1232REF

37 ADS1232REF Layout: Top

38 ADS1232REF Layout: Bottom Analog Digital Power

39 New Reference Designs and Tests

40 Schematic Signal path –RC filter, Ferrite bead, Schottky Diode Array Ferrite bead for input RF filtering RC filter with cut off frequency is about 36Hz(differential signal) Schottky Diode (Reverse Current 100nA) - Schottky Diode Reverse Current 100nA (Max) 100nA*2*1K*2%= 4uV(Worst case) Only half of 1LSB(9.54uV) - Due to the symmetry of signal path, the Reverse Current can be neglected

41 Schematic Analog and digital power –Analog and digital power are isolated with L1(100uH) inductor

42 Schematic All decoupling Cap C4,C8,C9,C10 are as close as possible to the decoupling points Series input resistance to limit current flow to analog inputs and supply pins

43 PCB Layout (Through-Hole)

44 PCB Layout (Thru-Hole) One ground for both Analog and digital A chassis “ground ring” In order to save PCB size and for good layout, flying wire is used over top layer to provide analog power supply Digital power Analog power

45 PCB Layout (SMD) Ground Plane on Bottom-side Filter: R=1Kohm,C3=2.2 uf, C1,C2=0.22uf, 2 Beads

46 Layout Benefits A chassis “ground ring” --additional EMI/RFI Filter components

47 Customer Layout Issues Undefined EMI Current Paths

48 Improved Layout

49 RFI and ESD Testing of New Design and Layouts

50 EMI/RFI Test IEC Test Level: Level 3 is the highest test level for weigh scale application

51 EMI/RFI Test IEC Test equipment: –Anechoic chamber, EMI filters, RF signal generator, Power amplifiers, An isotropic field sensor, etc. –For lab test, use Walkie Talkies to simulate the test environment.

52 EMI/RFI Test IEC For Lab test, Walkie Talkies Uniden GMR (0.5W,400MHz-500MHz) The transmitted power of radio transmitters is often specified in terms of ERP (effective radiated power) referred to a half-wave dipole. Therefore, the generated field strength, for the far field, can be directly obtained by the following dipole formula: The formula is for far field(d> ), Walkie Talkies operation frequency=467MHz, d>1m As estimation, still use this formula for near E field, for E=10V/m,d=21cm In the following test, 1) using d=7.5cm, E=28.3V/m 2) using d=1cm

53 EMI/RFI Test IEC Position 1 Position 2 Position 3 Position 4

54 Comparison of Results Position 1 Surface mount version Through hole version Customer RF Applied Here

55 Comparison of Results RF Applied Here Position 2 Surface mount version Through hole version PMS design RF Applied Here

56 Comparison of Results Position 3 Surface mount version Through hole version Customer RF Applied Here

57 Comparison of Results Position 4 Surface mount version Through hole version Customer RF Applied Here

58 EMI/RFI Test Results Positon 1Surface mountThrough holeCustomer ENOB Noise free bits Code shift Positon 2Surface mountThrough holeCustomer ENOB Noise free bits Code shift61780 Positon 3Surface mountThrough holeCustomer ENOB Noise free bits Code shift Positon 4Surface mountThrough holeCustomer ENOB Noise free bits Code shift52050

59 IEC ESD Test: IEC An example: table top equipment –Contact discharge to the conductive surfaces of EUT –Air discharge to the insulating surfaces of EUT –Contact discharge to horizontal and vertical coupling planes.

60 IEC ESD Test: IEC Standard ESD compliance test level: –Apply from the lower levels up to the required test level. –Include both positive and negative polarities at each level. –10 single discharges per polarity per level.

61 IEC ESD Test: IEC ESD result classification: 1) Normal performance within specification limits. 2) Temporary degradation or loss of function or performance which is self-recoverable. 3) Temporary degradation or loss of function or performance which requires operator intervention or system reset. 4) Degradation or loss of function which is not recoverable due to damage of equipment (components) or software, or loss of data.

62 IEC ESD Test: IEC IEC stress is applied to a finished product –Not all device need to be tested to this standard –IEC testing is not a part of the normal device qual requirements –On devices that do need to be tested, not all pins need to be tested Only pins which are accessible to the “outside world” need to pass this test. –Analog I/O ports –Digital I/O ports For weigh scale application( battery powered), Load cell, LCD display( not included in this design) expose to the “outside world”, ESD will get through Load cell connection wire to PCB

63 Reference Design ESD Test MINIZap MZ-15 ESD Gun Air Discharge mode –Simulates a fast approach hand/metal discharge –IEC Air Dsicharge ball tip TPA-2 Fast Rise Current Injection (CONTACT MODE ) –Provide current injection “equivalent” per IEC with a fast rising slope (Include the Model HBM-MZ-15) –IEC Contact Mode pointed TPC- 2A OMNI-TIP

64 Reference Design ESD Test IEC standard –Contact discharge to the conductive surfaces of EUT –Air discharge to the insulating surfaces of EUT Reference design test –Both Contact and Air discharge to the conductive sensor connection wire

65 Reference Design ESD Test Pass all level Contact discharge (+/-kv) Pass all positive level Air discharge (+kv) Fail -8, -15kv Air discharge –ESC+ fail( relate to pin of REFP, AVDD ) –Reading 7FFFF, in-recoverable, damaged

66 Reference Design ESD Test Fail negative Air discharge -8kv, -15kv, –add a 0.01uf cap between ESC+ and “ground ring” to provide a low impedance for ESD –change AVDD protection Resistor 10ohm to 25ohm PASS all level Contact and Air discharge test after change made 0.01uf Cap added between ESC+ to Chassis “ground ring” AVDD Protection Resistor Changes from 10ohm to 25ohm AVDD trace REFP trace Chassis “ground ring”

67 Customer Board ESD Test Passed several level Discharge Negative level Discharge has better performance over Positive Discharge

68 Reference Design ESD Tests The filter is using 0603 resistor and cap, during the ESD test, the 0603 resistor is dead before the device down. Change the 0603 resistor to higher power resistor ( through hole resistor)

69 Reference Design ESD Tests After changing the resistor –Pass all level Contact discharge (+/-kv) –Pass all level Air discharge (+kv)

70 Customer PCB Examples

71 Customer Example

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80 References Zhu, W., “ADS1230 EMI and RFI Test Report”, Texas Instruments Zhu, W., “ADS1230 ESD Test Report”, Texas Instruments Kuehl, T., “Tackling EMI and RFI at the Board and System Level”, Texas Instruments Johanson Dielectics, “X2Y for Decoupling Applications” Anderson, R., Downs, R., “Designing Low-Noise Bridge Measurement Systems“, Texas Instruments Kester, W., "Grounding (Again)", Analog Dialogue - Ask the Application Engineer, Hu, B.; See, K.Y., "Impact of analog/digital ground design on circuit functionality and radiated EMI," Electronic Packaging Technology Conference, EPTC Proceedings of 7th, vol.1, no., pp. 4 pp.-, 7-9 Dec Available at arnumber= &arnumber= &arSt=+4+pp.&ared=&arAuthor=Hu%2C+B.% 3B+See%2C+K.Y.http://ieeexplore.ieee.org/iel5/10751/33891/ pdf?isnumber=33891 Downs, R., "Analog-to-Digital Converter Grounding Practices Affect System Performance", Texas Instruments Application Note SBAA052, Ott, H. W., "Partitioning and Layout of a Mixed-Signal PCB", Printed Circuit Design, June 2001, pp :


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