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11-1 4446 Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology I/O System Design.

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Presentation on theme: "11-1 4446 Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology I/O System Design."— Presentation transcript:

1 11-1 4446 Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology I/O System Design

2 11-2  65,536 possible I/O ports  Data transfer between ports and the processor is over data bus  8088 uses address bus A[15:0] to locate an I/O port  AL (or AX) is the processor register that takes input data (or provide output data) I/O Data bus Address bus A[15:0] AL AX 8088 Introduction (cont’d)

3 11-3 Introduction I/O devices serve two main purposes –To communicate with outside world –To store data I/O controller acts as an interface between the systems bus and I/O device –Relieves the processor of low-level details –Takes care of electrical interface I/O controllers have three types of registers –Data –Command –Status

4 11-4 Introduction (cont’d)

5 11-5 Introduction (cont’d) To communicate with an I/O device, we need –Access to various registers (data, status,…) This access depends on I/O mapping –Two basic ways »Memory-mapped I/O »Isolated I/O –A protocol to communicate (to send data, …) Three types –Programmed I/O –Direct memory access (DMA) –Interrupt-driven I/O

6 11-6 Accessing I/O Devices I/O address mapping –Memory-mapped I/O Reading and writing are similar to memory read/write Uses same memory read and write signals Most processors use this I/O mapping –Isolated I/O Separate I/O address space Separate I/O read and write signals are needed Pentium supports isolated I/O –64 KB address space »Can be any combination of 8-, 16- and 32-bit I/O ports –Also supports memory-mapped I/O Memory addressing space I/O addressing space I/O Memory addressing space 00000 FFFFF 0000 FFFF 00000 FFFFF Direct I/OMemory-mapped I/O

7 11-7 Accessing I/O Devices (cont’d) Accessing I/O ports in 80x86 –Register I/O instructions in accumulator, port8 ; direct format –Useful to access first 256 ports in accumulator,DX ; indirect format –DX gives the port address –Block I/O instructions ins and outs –Both take no operands---as in string instructions ins : port address in DX, memory address in ES:(E)DI outs : port address in DX, memory address in ES:(E)SI We can use rep prefix for block transfer of data

8 11-8 8088 Port Addressing Space  Addressing Space FFFF 0000 00F8 00FF Accessed directly by instructions Accessed through DX  Accessing directly by instructions IN AL, 80H IN AX, 6H OUT 3CH, AL OUT 0A0H, AX  Accessing through DX IN AL, DX IN AX, DX OUT DX, AL OUT DX, AX

9 11-9 Input Port Implementation 8088 Data Bus Address bus Decoder Input Gating device Other control signals — The outputs of the gating device are high impedance when the processor is not accessing the input port — When the processor is accessing the input port, the gating device transfers input data to CPU data bus — The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus

10 11-10 Input Port Implementation  Circuit Implementation — Assume that the address of the input port is 9CH Data busInput data Tri-state buffer CE RDIO/M A7 A6 A5 A4 A3 A2 A1 A0

11 11-11 Input Port Implementation

12 11-12 Output Port Implementation  Circuit Implementation — Assume that the address of the output port is 9CH Data busOutput dataLatch CLK WRIO/M A7 A6 A5 A4 A3 A2 A1 A0

13 11-13 Output Port Implementation

14 11-14 A Reconfigurable Port Decoder 1Vcc

15 11-15 An Example I/O Device Keyboard –Keyboard controller scans and reports –Key depressions and releases Supplies key identity as a scan code –Scan code is like a sequence number of the key »Key’s scan code depends on its position on the keyboard »No relation to the ASCII value of the key –Interfaced through an 8-bit parallel I/O port Originally supported by 8255 programmable peripheral interface chip (PPI)

16 11-16 An Example I/O Device (cont’d) 8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC) –These ports are mapped as follows 8255 register Port address PA (input port)60H PB (output port)61H PC (input port)62H Command register63H

17 11-17 An Example I/O Device (cont’d) Mapping of 8255 I/O ports

18 11-18 An Example I/O Device (cont’d) Mapping I/O ports is similar to mapping memory –Partial mapping –Full mapping Keyboard scan code and status can be read from port 60H –7-bit scan code is available from PA0 – PA6 –Key status is available from PA7 PA7 = 0 – key depressed PA0 = 1 – key released

19 11-19 I/O Data Transfer Data transfer involves two phases –A data transfer phase It can be done either by –Programmed I/O –DMA –An end-notification phase Programmed I/O Interrupt Three basic techniques –Programmed I/O –DMA –Interrupt-driven I/O

20 11-20 I/O Data Transfer (cont’d) Programmed I/O –Done by busy-waiting This process is called polling Example –Reading a key from the keyboard involves Waiting for PA7 bit to go low –Indicates that a key is pressed Reading the key scan code Translating it to the ASCII value Waiting until the key is released

21 11-21 8255 Programmable Peripheral Interface

22 11-22 8255 Programmable Peripheral Interface Data bus 8088 D[7:0] A0 A1 RD WR RESET CS Control port PA[7:0] PB[7:0] PC[7:0] A7 A6 A5 A4 A3 A2 IO/M A1 A0 Port 0 0 1 1 0 1 PA PB PC Control

23 11-23 8255 Programmable Peripheral Interface

24 11-24 Programming 8255  8255 has three operation modes: mode 0, mode 1, and mode 2

25 11-25 Programming 8255  Mode 0: — Ports A, B, and C can be individually programmed as input or output ports — Port C is divided into two 4-bit ports which are independent from each other  Mode 1: — Ports A and B are programmed as input or output ports — Port C is used for handshaking PA[7:0] STB A IBF A INTR A PC3 PC5 PC4 PB[7:0] STB B IBF B INTR B PC0 PC1 PC2 PC6, 7 8255 PA[7:0] OBF A ACK A INTR A PC3 PC6 PC7 PB[7:0] OBF B ACK B INTR B PC0 PC1 PC2 PC4, 5 8255



28 11-28 Programming 8255  Mode 2: — Port A is programmed to be bi-directional — Port C is for handshaking — Port B can be either input or output in mode 0 or mode 1 PA[7:0] OBF A ACK A INTR A PC4 PC6 PC7 STB A IBF A PC0 PC3 PC5 8255 PC0 PB[7:0] In Out Mode 0 STB B OBF B IBF B ACK B INTR B Mode 1 1.Can you design a decoder for an 8255 chip such that its base address is 40H? 2.Write the instructions that set 8255 into mode 0, port A as input, port B as output, PC0-PC3 as input, PC4-PC7 as output ?

29 Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1 Strobed Output Timing diagrams.

30 11-30 Example: Mode 1 Input BIT5EQU 20H PORTCEQU22H PORTAEQU20H READ PROCNEAR Read: –IN AL, PORTC; read portc –TEST AL, BIT5;test IBF –JZ Read;if IBF=0 –IN AL, PORTA;Read Data READ ENDP keyboard PA0 PA7 STB PC4DAV 8255

31 11-31 Example: Mode 1 output Printer PB0 PB7 ACK PC2ACK 8255 PC4DS Data Strobe : to tell the printer to latch the incoming data. Generated Externally

32 11-32 BIT1EQU2 PORTCEQU62H PORTBEQU61H CMDEQU63H PRINTPROCNEAR ; check printer ready? IN AL, PORTC ;get OBF TEST AL, BIT1 ;test OBF JZ PRINT ;if OBF=0 buffer is full ;send character to printer MOV AL, AH ;get data OUT PORTB, AL ;print data ; send data strobe to printer MOV AL, 8 ;clear DS OUT CMD, AL MOV AL, 9 ;clear DS OUT CMD, AL ;rising the data at the positive edge of DS RET PRINT ENDP Example: Mode 1 output

33 11-33 Keyboard example 1/2

34 11-34 Keyboard example 2/2

35 11-35 Bouncing Problem

36 11-36 Bouncing

37 11-37 Software Solution

38 11-38 De-bouncing Circuitry Two asynchronous flip-flop solutions are given below The basic idea is that these flip-flops store the values even if the D/D nodes both float

39 11-39 Another Solution

40 11-40 External Interface Two ways of interfacing I/O devices –Serial Cheaper Slower –Parallel Faster Data skew Limited to small distances

41 11-41 External Interface (cont’d) Two basic modes of data transmission

42 11-42 External Interface (cont’d) Serial transmission –Asynchronous Each byte is encoded for transmission –Start and stop bits No need for sender and receiver synchronization –Synchronous Sender and receiver must synchronize –Done in hardware using phase locked loops (PLLs) Block of data can be sent More efficient –Less overhead than asynchronous transmission Expensive

43 11-43 External Interface (cont’d)

44 11-44 External Interface (cont’d) Asynchronous transmission

45 11-45 External Interface (cont’d) EIA-232 serial interface –Low-speed serial transmission –Adopted by Electronics Industry Association (EIA) Popularly known by its predecessor RS-232 –It uses a 9-pin connector DB-9 Uses 8 signals –Typically used to connect a modem to a computer

46 11-46 External Interface (cont’d) Transmission protocol uses three phases –Connection setup Computer A asserts DTE (Data Terminal Equipment) Ready –Transmits phone# via Transmit Data line (pin 2) Modem B alerts its computer via Ring Indicator (pin 9) –Computer B asserts DTE Ready (pin 4) –Modem B generates carrier and turns its DCE (Data Communication Equipment) Ready Modem A detects the carrier signal from modem B –Modem A alters its computer via Carrier Detect (pin 1) –Turns its DCE Ready –Data transmission Done by handshaking using –request-to-send (RTS) and clear-to-send (CTS) signals –Connection termination Done by deactivating RTS

47 11-47 External Interface (cont’d) Parallel printer interface –A simple parallel interface –Uses 25-pin DB-25 8 data signals –Latched by strobe (pin 1) Data transfer uses simple handshaking –Uses acknowledge (CK) signal »After each byte, computer waits for ACK 5 lines for printer status –Busy, out-of-paper, online/offline, autofeed, and fault Can be initialized with INIT –Clears the printer buffer and resets the printer

48 11-48 External Interface (cont’d)

49 11-49 Serial Data Transfer  Asynchronous v.s. Synchronous — Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication — Synchronous transfer does not transfer extra bits. However, it requires clock signal Frame Start bit B0B1B2B3B4B5B6 Parity Stop bits Asynchronous Data transfer Synchronous Data transfer clk data B0B1B2B3B4B5 data Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).

50 11-50 8251 USART Interface A7 A6 A5 A4 A3 A2 A1 IO/M D[7:0] RD WR A0C/D CLK TxC RxC TxD RxD 8251 RS232

51 11-51

52 11-52 Programming 8251  8251 mode register 76543210 Mode register Number of Stop bits 00: invalid 01: 1 bit 10: 1.5 bits 11: 2 bits Parity 0: odd 1: even Parity enable 0: disable 1: enable Character length 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits Baud Rate 00: Syn. Mode 01: x1 clock 10: x16 clock 11: x64 clock

53 11-53 Programming 8251  8251 command register EHIRRTSERSBRKRxEDTRTxE command register TxE:transmit enable DTR:data terminal ready, DTR pin will be low RxE:receiver enable SBPRK:send break character, TxD pin will be low ER:error reset RTS:request to send, CTS pin will be low IR:internal reset EH:enter hunt mode

54 11-54 Programming 8251  8251 status register DSR SYNDE TFEOEPE TxEMPTY RxRDYTxRDY status register TxRDY:transmit ready RxRDY:receiver ready TxEMPTY:transmitter empty PE:parity error OE:overrun error FE:framing error SYNDET:sync. character detected DSR:data set ready

55 11-55 Simple Serial I/O Procedures  Read start Check RxRDY Is it logic 1? Read data register* end Yes No * This clears RxRDY  Write start Check TxRDY Is it logic 1? Write data register* end Yes No * This clears TxRDY

56 11-56 Errors –Parity error: Received data has wrong error -- transmission bit flip due to noise. –Framing error: Start and stop bits not in their proper places. This usually results if the receiver is receiving data at the incorrect baud rate. –Overrun error: Data has overrun the internal receiver FIFO buffer. Software is failing to read the data from the FIFO.

57 11-57 Programmable Timer 8254

58 11-58 8254 Programming

59 11-59 8254 Programming Each counter may be programmed with a count of 1 to FFFFH. –Minimum count is 1 all modes except 2 and 3 with minimum count of 2. Each counter has a program control word used to select the way the counter operates. –If two bytes are programmed, then the first byte (LSB) stops the count, and the second byte (MSB) starts the counter with the new count.

60 11-60 8254 Read Back Command  8254 Read Back Command 1 1 COUNTSTATUSCNT2 CNT1 CNT00 NULL COUNT: goes low when the new count written to a counter is actually loaded into the counter  8254 status word format OUTPUT NULL COUNT RW1RW0M2 M1 M0BCD

61 11-61 8254 Modes Mode 0: An events counter enabled with G. –The output becomes a logic 0 when the control word is written and remains there until N plus the number of programmed counts. Mode 1: One-shot mode. –The G input triggers the counter to output a 0 pulse for `count' clocks. –Counter reloaded if G is pulsed again.

62 11-62 8254 Modes Mode 2: Counter generates a series of pulses 1 clock pulse wide. –The seperation between pulses is determined by the count. –The cycle is repeated until reprogrammed or G pin set to 0. –Mode 3: Generates a continuous square-wave with G set to 1. If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.

63 11-63 8254 Modes Mode 4: Software triggered one-shot –(G must be 1). Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

64 11-64 Motor Control

65 11-65 Motor Control

66 11-66

67 11-67 DMA Direct memory access (DMA) –Problems with programmed I/O Processor wastes time polling –In our example »Waiting for a key to be pressed, »Waiting for it to be released May not satisfy timing constraints associated with some devices –Disk read or write –DMA Frees the processor of the data transfer responsibility

68 11-68 DMA Example A hard disk data transfer rate of 5MB/s –One byte every 200 ns !! A microprocessor hardly can execute even one instruction in 200 ns. –Multiple instructions would be required to accomplish data transfer read the byte from the hard disk place it in memory increment a memory pointer test for another byte to read

69 11-69 DMA

70 11-70 DMA DMA is implemented using a DMA controller –DMA controller Acts as slave to processor Receives instructions from processor Example: Reading from an I/O device –Processor gives details to the DMA controller »I/O device number »Main memory buffer address »Number of bytes to transfer »Direction of transfer (memory  I/O device, or vice versa)

71 11-71 DMA Steps in a DMA operation –Processor initiates the DMA controller Gives device number, memory buffer pointer, … –Called channel initialization Once initialized, it is ready for data transfer – When ready, I/O device informs the DMA controller DMA controller starts the data transfer process –Obtains bus by going through bus arbitration –Places memory address and appropriate control signals –Completes transfer and releases the bus –Updates memory address and count value –If more to read, loops back to repeat the process –Notify the processor when done Typically uses an interrupt

72 11-72 I/O Data Transfer (cont’d) DMA controller details

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