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IKI10201 04b-Simplification of Boolean Functions Bobby Nazief Semester-I 2005 - 2006 The materials on these slides are adopted from Prof. Daniel Gajski’s transparency for Principles of Digital Design.

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2 Tabulation Method Map method is a trial-and-error procedure Tabulation method performs thorough search It starts with SOM and consists of 2 steps: – PIs generation group minterms by number of 1s compare minterms & find pairs that differ in 1 variable generate subcubes repeat the above 3 steps to generate subcubes until no more subcubes can be generated – Minimal cover generation find EPIs through a selection table find minimal cover through the POS of PIs

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3 K-map representation: PIs generation: – 0-subcubes Example: simplify w’y’z’ + wz + xyz + w’y yz wx

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4 – 1-subcubes – 2-subcubes Example: simplify w’y’z’ + wz + xyz + w’y (cont.)

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5 Minimal cover generation: – EPIs selection PI list:w’z’, w’y, yz, wz EPI list:w’z’, wz POS:(P 2 + P 3 )(P 2 + P 3 ) = P 2 + P 3 – Minimal cover expressions: F1 = w’z’ + wz + w’y F2 = w’z’ + wz + yz Example: simplify w’y’z’ + wz + xyz + w’y (cont.)

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6 K-map representation: PIs generation: – 0-subcubes, 1-subcubes Another example yz wx

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7 Minimal cover generation: – EPIs selection PI list:w’yz’, x’y’z, w’xy, wx’z, xyz, wyz EPI list:w’yz’, x’y’z POS:(P 3 + P 5 )(P 4 + P 6 )(P 5 + P 6 ) = (P 3 + P 5 )(P 4 P 5 + P 5 P 6 + P 4 P 6 + P 6 ) = P 3 P 4 P 5 + P 4 P 5 + P 3 P 6 + P 5 P 6 – Minimal cover expressions: F1 = w’yz’ + x’y’z + wx’z + xyz F2 = w’yz’ + x’y’z + w’xy + wyz F3 = w’yz’ + x’y’z + xyz + wyz Another example (cont.)

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8 Technology Mapping for Gate Arrays Gate arrays contain only one type of m-input gate (such as 3-input NAND, 3-input NOR) Technology mapping is a transformation of Boolean expressions into a logic schematic containing only this type (NAND or NOR) of gate – SOP/POS NAND/NOR gate implementation

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9 Conversion & Optimization Conversion: Optimization: Conversion procedure: replace AND & OR gates with NAND (NOR) gates by using Rules 1 & 2 (3 & 4), and eliminate double inverters whenever possible

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10 Translation standard forms to NAND/NOR schematics

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11 Conversion to NAND (NOR) gates

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12 Technology Mapping for Custom Libraries Libraries contain gates with different functions and different delays Technology mapping means covering schematic with library gates Minimize delay on critical paths Minimize cost on non-critical paths

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13 Example design with custom libraries F = w’z’ + z(w + y) AND-OR implementation (delay = 7.2ns, cost = 28) NAND implementation (delay = 5.2ns, cost = 22)

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14 Example design with custom libraries (cont.) Alternatif A (delay = 5.4ns, cost = 20) Alternatif B (delay = 3.8ns, cost = 20) Alternatif B-optimized (delay = 3.8ns, cost = 18)

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15 Design with static 1-hazard Timing Diagram

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16 Hazard-free design Timing Diagram

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