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Published byJoel Thomasson Modified over 9 years ago
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パイプライン化してない PICO ALU pc ir register file mar mdr Address busData bus Memory Controller
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PICO のパイプライン構造 Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm.
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Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm. LDLI r1,#1
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Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm. LDLI r2,#2LDLI r1,#1
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Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm. LDLI r3,#3LDLI r2,#2LDLI r1,#1 1
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Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm. ADD r1,#2LDLI r2,#2LDLI r1,#1 2 1 LDLI r3,#3
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Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm. ADD r2,r2LDLI r3,#3LDLI r2,#2 3 2 ADD r1,#2
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Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm. ADD r2,r2LDLI r3,#3 3 3 ADD r1,#2
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Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm. ADD r2,r2 4 3 ADD r1,#2
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Instruction Memory + Data Memory ALU 2 IFRF EXWB IFPC RFPC IFIRRFIR wadr rega regb regc a b c Imm. ADD r2,r2 4
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