Presentation on theme: "CSC2420 1 Tutorial 11 The Microprocessor and its Architecture."— Presentation transcript:
CSC2420 1 Tutorial 11 The Microprocessor and its Architecture
Tutorial 11 By Ivan Leung2 Objectives Revision on lecture note(CPU Architecture) Intel x86
Tutorial 11 By Ivan Leung3 CPU What is CPU? one central unit that executes program instructions communicates with and controls the operation of other subsystems within the computer its main function – to fetch and execute instructions
Tutorial 11 By Ivan Leung5 CPU Fundamental As you know, fetching and execution are broken down into smaller steps(e.g. movement between registers, addition by using ALU, etc…) Each of these smaller steps is a machine code, i.e. an assembly instruction Assembly program will be assembled to machine instructions and then put in the main memory (You should know that already, Right?)
Tutorial 11 By Ivan Leung6 CPU Fundamental Depends on the machine instruction, the CPU will generate a set of control signals to control other subsystem (You also known that) CPU bus(What is bus?) The bus is internal to the CPU connected the components in the CPU (e.g. ALU, GPR, MAR, MDR, PC, …)
Tutorial 11 By Ivan Leung7 CPU To main memory From control unit CPU internal bus From control unit Memory Function Completion: indicates the operation in memory is completed CPU with Single-bus Y,Z and TEMP are registers. That are transparent to programmers. CPU will use it by itself.
Tutorial 11 By Ivan Leung8 Example of Bus organization Fetch a Word from MM Assume the address of the memory location to be accessed is in R1 and the memory data are to be loaded into R2 Write a Word to MM 1.MAR <= [R1] 2.Read (control to memory) 3.Wait for MFC from memory 4.R2 <= [MDR] 1.MAR <= [R1] 2.MDR <= [R2], Write signal to control 3.Wait for MFC from memory CPU idle
Tutorial 11 By Ivan Leung9 Control signals To MM: Read, Write, Reset, etc To Registers: Ri in – input data to Ri from CPU bus if ‘1’ Ri out – output data in Ri to CPU bus if ‘1’; ‘0’: bus is used by others reset, etc… To ALU: Add, Sub, Mul, Div, etc…
Tutorial 11 By Ivan Leung10 Example of Control Signals Add data in R1 and R2 registers and put the result to R3 1.R1 out,Y in 2.R2 out, Add, Z in 3.Z out, R3 in Electronic switch: In control ‘1’ will get input else will not Out control ‘1’ will output the data else ‘0’ will not
Tutorial 11 By Ivan Leung11 1-bit register with Switch SR latch (God! What is it?) Control to SR latch Z means the tri-state is in high impedance mode
Tutorial 11 By Ivan Leung12 Control Sequence ADDA,R1 1.PC out,MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in Load [PC] into MAR; Send Read request to the memory; Reset Y to all ‘0’s Load [PC], 0 to ALU inputs, operate PC+1 and write result to Z 2.Z out,PC in, WMFC Load [Z] to PC wait for memory to complete 3.MDR out,IR in Got data in MDR from MM and load it to IR 4.IR out,MAR in, Read Load address of A to MAR Send Read request to the memory 5.R1 out,Y in, WMFC Load [R1] to Y and further to ALU wait for memory to complete 6.MDR out,Add,Z in Got data in MDR from MM and load it to ALU, add it to [Y], and write result to Z 7.Z out,R1 in,EndLoad [Z] to R1 Fetch Execution
Tutorial 11 By Ivan Leung13 Control Sequence BRN(conditional/unconditional) 1.PC out,MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in Load [PC] into MAR; Send Read request to the memory; Reset Y to all ‘0’s Load [PC], 0 to ALU inputs, operate PC+1 and write result to Z 2.Z out,PC in, WMFC Load [Z] to PC wait for memory to complete 3.MDR out,IR in Got data in MDR from MM and load it to IR 4.PC out, Y in Load branch address to Y and further to ALU 5.IR out, Add, Z in Load [IR] to ALU and add it to [Y], put the result to Z 6.Z out,PC in,EndLoad [Z] to PC For step 4, if not satisfy branch condition, then End branch address = [PC] + Offset
Tutorial 11 By Ivan Leung14 CPU with 3 internal buses required significantly fewer control steps ADDR1,R2,R3 (one clock cycle) execution phase to be performed in one clock cycle Y is not required because ALU can take two inputs from two registers from two data buses Z is not required because ALU can write the result to the destination register by 3 rd bus performs register-to-register operations in a single clock cycle
Tutorial 11 By Ivan Leung16 Control Signal But how to generate the control signals as the control sequence discussed before? By microprogramming What is microprogramming? Using a sequence of microinstructions to generates a sequence of control signals
Tutorial 11 By Ivan Leung17 Microprogramming A control word(CW) is a word whose individual bits represent the various control signals Each CW represents a set of control signals in one step of control sequence of an instruction, which is called microinstruction A sequence of CWs, which is referring to the control sequence of a machine instruction, is called microroutine Microprogram memory contains the microroutine of all instructions Depends on [IR], a starting address of corresponding microroutine is given to microprogram counter MicroPC will be incremented and then a sequence of CWs will be given out
Tutorial 11 By Ivan Leung18 Hand-shaking with Memory In the control sequence, there are steps that have to wait for MFC from memory. A signal WMFC is used.
Tutorial 11 By Ivan Leung19 Hand-shaking with Memory Why MR? if But, if it starts at (i+1)-th pulse, However, after the drop of (i+1)-th pulse and before the raise of (i+2)-th pulse, It is wrong!
Tutorial 11 By Ivan Leung21 8086 (Review) 16-bit processor with 20-bit address bus Direct mode addressing with memory space of 1MByte 14 words by 16-bit register set (You should be familiar with them) Byte addressable For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location
Tutorial 11 By Ivan Leung23 8086 Why there is no Program Counter(PC)? How to indicate the next instruction to be executed? How stack works? What is the function of SP? What is the starting position of SP? How “CALL” works? How to jump to other procedure? How to return(RET) to previous procedure?