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Fakultät für informatik informatik 12 technische universität dortmund Flash Memory Jian-Jia Chen (Slides are based on Yuan-Hao Chang) TU Dortmund Informatik.

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Presentation on theme: "Fakultät für informatik informatik 12 technische universität dortmund Flash Memory Jian-Jia Chen (Slides are based on Yuan-Hao Chang) TU Dortmund Informatik."— Presentation transcript:

1 fakultät für informatik informatik 12 technische universität dortmund Flash Memory Jian-Jia Chen (Slides are based on Yuan-Hao Chang) TU Dortmund Informatik 12 Germany 2015 年 01 月 27 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply. © Springer, 2010

2 - 2 - technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Why Flash Memory Diversified Application Domains  Portable Storage Devices  Consumer Electronics  Industrial Applications  Critical System Components

3 - 3 - technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Layout of Flash Memory … (2KB + 64 Byte) … (2KB + 64 Byte) … (2KB + 64 Byte) Page: basic write- operation unit. 063 … … Block: basic erase- operation unit. 128MB Flash Memory

4 - 4 - technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Characteristics of Flash Memory Write-Once  No writing on the same page unless its residing block is erased!  Pages are classified into valid, invalid, and free pages. Bulk-Erasing  Pages are erased in a block unit to recycle used but invalid pages. Wear-Leveling  Each block has a limited lifetime in erasing cycles. E.g., 10,000 ~ 100,000 erase cycles for each block

5 - 5 - technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Terminology Valid data: the latest version of data stored in flash Invalid data: not the latest version of data stored in flash Live page: a page that stores valid data Dead page: a pages that stores invalid data Free page: a page that is erased and is ready to store data Free block: a block that is erased and is not allocated to store any data Hot data: frequently updated data  Valid hot data might become invalid in the near future. Cold data: non-frequently updated data  Valid cold data might stay in the same place for a long time.

6 - 6 - technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Dead pages ABCDAB Management Issues – Flash-Memory Characteristics Example 1: Out-place Update

7 - 7 - technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 A live page A dead page A free page This block is to be recycled. (3 live pages and 5 dead pages) LDDLDDLD LLDLLLFD LFLLLLDF FLLFLLFD Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection

8 - 8 - technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 LLDLLLD LFLLLLD LLFLLFD L L DDDD A live page A dead page A free page Live data are copied to somewhere else. L DDDD Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection

9 - 9 - technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 A live page A dead page The block is then erased. Overheads: live data copying block erasing. LLDLLLD LFLLLLD LLFLLFD L L FFFFFFFF L Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection

10 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Management Issues – Flash-Memory Characteristics Example 3: Wear-Leveling LDDLDDLD LLDLLLFD LFLLLLDF FLLFLLFD Erase cycle counts Wear-leveling might interfere with the decisions of the block- recycling policy. A live page A dead page A free page A B C D

11 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Single-Level Cell (SLC) vs. Multiple-Level Cell (MLC) A limited bound on erase cycles  SLC : 100,000  MLC x2 : 10,000 Bit error probability  SLC:  MLC: 10 -6

12 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 MLC vs. SLC (Cont.) Electronic Engineering Times, July 2005

13 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Price and Read/Write Performance NORNAND SLCNAND MLC x2 Price34.55 $/GB6.79 $/GB2.48 $/GB Read23.84 MB/sec15.33 MB/sec13.5 MB/sec Write0.07 MB/sec4.57 MB/sec2.34 MB/sec Erase0.22 MB/sec85.33 MB/sec MB/sec * NOR: Silicon Storage Technology (SST). NAND SLC: Samsung Electronics. K9F1G08Q0M. NAND MLCx2: ST STMicroelectronics [1,2] 1. Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, and Cheng-Chih Yang, "A NOR Emulation Strategy over NAND Flash Memory," the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Daegu, Korea, August 21-24, Yuan-Hao Chang and Tei-Wei Kuo, “A Log-based Management Scheme for Low-cost Flash-memory Storage Systems of Embedded Systems”

14 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Flash Memory Management Management issues  Write constraints imposed by flash memory  Scalability issue  Garbage collection  Performance considerations Reliability issues  Cell error rate problem imposed by MLC flash memory  Error correction coding vs. wear leveling  Read/write disturbance problem  Data retention problem

15 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Typical System Architecture

16 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 FTL adopts a page-level address translation mechanism.  The main problem of FTL is on large memory space requirements for storing the address translation information. Flash Translation Layer (FTL)

17 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 A logical address under NFTL is divided into a virtual block address and a block offset.  e.g., LBA=1019 => virtual block address (VBA) = 1019 / 8 = 127 and block offset = 1019 % 8 = (9,23) Write data to LBA= NFTL Address Translation Table (in main-memory) Free Used Free Used Free A Primary Block Address = 9 A Replacement Block Address = 23 VBA=127 Block Offset=3 If the page has been used Write to the first free page NAND Flash Translation Layer (NFTL)

18 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 FTL or NFTL FTLNFTL Memory Space RequirementsLargeSmall Address Translation TimeShortLong Garbage Collection OverheadLessMore Space UtilizationHighLow The memory-space requirements for one 1GB NAND (2KB/Page, 4B/Table Entry, 128 Pages/Block) –FTL: 2MB (= 4*(1024*1024*1024)/2K) –NFTL: 32KB (= 2*4*(1024*1024*1024)/(2K * 128))

19 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Size of Translation Tables 1GB32GB1TB32TB FTL2MB64MB2GB64GB NFTL32KB1MB32MB1GB No matter which kind of granularity of address translation is adopted, the fast growing flash memory capacity would eventually make the translation table too large to be fitted in RAM.

20 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Adaptive Two-Level Mapping Mechanism The coarse-grained hash table maintains the primary block and its replacement block  This will be mainly used to identify the primary and replacement blocks The fine-grained hash table has limited entries to store the excessive live pages in the replacement block When the fine-grained table is full, the replacement policy has to be considered to move some pages to the coarse-grained table Improve the space utilization.  The delayed recycling of any primary block lets free pages of a primary block be likely used in the future. Chin-Hsien Wu and Tei-Wei Kuo, 2006, “An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems,” IEEE/ACM 2006 International Conference on Computer-Aided Design (ICCAD), November 5-9, 2006.

21 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 New Write Constraints of MLC Flash Write constraints  Pages can only be written sequentially in a block.  Partial page write/programming is prohibited. Impact on NFTL  Data can’t be written to any free page of primary blocks. The space utilization in primary blocks is even lower. Most writes are forced to be placed in the replacement block.  Pages of invalid data can’t be marked as dead. Each read operation should scan pages of the replacement block.

22 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Intuitive and Practical Solution Level-paging translation tables  Pages of translation tables are stored in flash, and are cached in RAM. Problems:  Hit ratio of cached pages  Extra page reads and writes for translation information  Crash recovery for translation table and lost data

23 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Performance Considerations MLC flash has growing market share:  Reason: low cost and high density  Drawbacks: low speed, low endurance, and low reliability Solutions:  Hardware multi-channel programming  Software multi-bank or multi-channel programming

24 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Wear Leveling Erase Cycles No Wear Leveling Dynamic Wear Leveling Physical Block Addresses (PBA) Perfect Static Wear Leveling Intuitive Static Wear Leveling

25 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Static Wear Leveling Random policy  It randomly select a block to reclaim after a fixed number of block erases or write requests.  It doesn’t track the locality of data acceses, such that it might move hot data that might turn dead in the near future.

26 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Static Wear Leveling (Cont.) Random policy with block-erasing table  Each-bit flag of the table is to indicate whether the corresponding blocks have been erased.  Whenever the block erases are not even enough, select blocks whose corresponding bit flag are not set. Pros and Cons:  Pros: it can identify the locality of data accesses.  Cons: the block-erasing table needs extra RAM space even it is comparatively small. Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo: Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design. DAC 2007:

27 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 The Block Erasing Table (BET) A bit-array: Each bit is for 2 k consecutive blocks.  Small k – in favor of hot-cold data separation  Large k – in favor of small RAM space Flash BET k=0 k=2 e cnt =0 f cnt =0 e cnt =0 f cnt =0 e cnt =1 f cnt =1 e cnt =2 f cnt =2 e cnt =3 f cnt =2 e cnt =1 f cnt =1 e cnt =2 f cnt =2 e cnt =3 f cnt =2 e cnt =4 f cnt =2 : a block that has been erased in the current resetting interval : an index to a block that the Cleaner wants to erase f cnt : the number of 1’s in the BET e cnt : the total number of block erases done since the BET is reset

28 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 e cnt =1998 f cnt =2 An unevenness level (e cnt / f cnt ) >= T  Triggering of the SW Leveler Resetting of BET when all flags are set. A SimpleStatic-Wear Leveler : A block that has been erased in the current resetting interval 1 1 k=2 : An index to a block that the Cleaner wants to erase f cnt : The number of 1’s in the BET e cnt : the total number of block erases since the BET is erased T : A threshold, T=1000 in this example : An index in the selection of a block set e cnt =1999 f cnt =2 e cnt =2000 f cnt = / 2 = 1000 >= 1000 (E cnt / f cnt >= T) 1 : An index that SW Leveler triggers the Cleaner to do garbage collection The Cleaner is triggered to 1. Copy valid data of selected block set to free area, 2. Erase block in the selected block set, and 3. Inform the Allocator to update the address mapping between LBA and PBA After a period of time, the total erase count reaches e cnt =2004 f cnt =3 e cnt =2998 f cnt =3 e cnt =2999 f cnt =3 e cnt =3000 f cnt = / 3 = 1000 >= 1000 (E cnt / f cnt >= T) 1 e cnt =3004 f cnt =4 After a period of time, the total erase count reaches e cnt =3999 f cnt =4 e cnt =4000 f cnt = / 4 = 1000>=1000 (e cnt / f cnt >=1000), but all flags in BET are 1  reset BET Reset to a randomly selected block set (flag) e cnt =0 f cnt =0

29 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Main-Memory Requirements 512MB1GB2GB4GB8GB k=0256B512B1024B2048B4096B k=1128B256B512B1024B2048B k=264B128B256B512B1024B k=332B64B128B256B512B MLC x2 (1 page = 2 KB, 1 block=128 pages)

30 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 File-System Considerations - Observations File systemNTFSFAT Number of write requests24,513179,670 Time taken (min:sec)4:3354:21 File systemNTFSFAT Number of read requests14,56823,528 Time taken (min:sec)2:533:19 Number of files19,535 Number of directories1,200 Average file size11 KB Archive size215,666 KB Archive: Linux source Write the files to a removable storage device Read the files from a removable storage device FAT file systems introduce excessive write requests! why ? FAT is the default file system for removable storage devices

31 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 File-System Considerations - Observations (Cont.) FAT #1 FAT #2 Content of File Directory Entry FAT #1 FAT #2 Content of File Directory Entry File #1 File #2 Layout of FAT filesystem LBA 0 https://www.pjrc.com/tech/8051/ide/fat32.html

32 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 File-System Considerations USB Flash Drives Card Readers Flash Memory Cards Host Applications Host Storage Media Device Controller Device Storage Media Device (a)(b) File System Drivers Operating System API Device Drivers Bus Drivers Filter Drivers Device Controller Disk Drivers

33 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Overview Cache Transport Unit Debug Unit Dispatch Unit Debug Viewer USB Mass Storage Device Driver USB Bus Driver Filesystem Identifier I/O Request Partition Table & Boot Sectors File System Layout I/O Request Trace Read and Write IoPackets I/O Response I/O Response Other IoPackets Filter Driver FIFO Queue Notifications When ? Cohesive- caching algorithm

34 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 The “Allow/Prevent Medium Removal” Operation Code in the USB Bulk-Only Transport … hrtimer.c intermodule.c itimer.c kallsyms.c … Write10 LBA=1446 LEN=1 Success … … … … … FAT File System USB Bus 1 st FAT 2 nd FAT File Content Directory Entry W W W W W … … Disk … … Allow Medium Removal Prevent Medium Removal Success USB Mass Storage Class, Bulk-Only Transport Protocol CBW: Command Block Wrapper CSW: Command Status Wrapper USB Mass Storage Device Driver Disk Driver An IoPacketSend a notification

35 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Worsening Reliability - Narrow Threshold Voltage Window MLC/TLC/QLC technology must squeeze the available window of threshold voltage for each logical state  Higher Bit Error Rate  Lower Endurance Source: SLC MLC

36 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Reliability Issues The low-cost MLC flash  Has lower erase cycles  Has higher and higher bit error rate. Ways to improve reliability  Error correction coding (ECC)  passively Non-erasure code such as BCH and RS  Wear leveling  positively Distribute block erases as even as possible Note: Erasure code is used in communication Non-erasure code is used in storage systems

37 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Error Correction Coding Error correction code of a page is stored in its spare area.  The time on error correction might be affected by the location of error bits or the number of error bits.  The space of the ECC hardware is increased as the number of supported error bits increases. Trend of MLC flash  The page size is getting larger  The bit error rate is getting higher Fast erasing bits  The fast worn-out flash cells VtVt

38 technische universität dortmund fakultät für informatik  Y.Chang and J. Chen, informatik 12, 2015 Data Retention Problem The guaranteed data retention: 10 years As the cell size is getting smaller, the number of electrons in the floating gate of a flash cell is getting smaller.  For example: A programmed cell can store 10,000 electrons. A lost of only 10% in this number can lead to a wrong read.  A loss of less than 2 electrons per week can be tolerated.


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