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Bob Hirosky, UVa 7/27/01  Level 2 Processor Status  Bob Hirosky The University of Virginia 

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Presentation on theme: "Bob Hirosky, UVa 7/27/01  Level 2 Processor Status  Bob Hirosky The University of Virginia "— Presentation transcript:

1 Bob Hirosky, UVa 7/27/01  Level 2 Processor Status  Bob Hirosky The University of Virginia 

2 Bob Hirosky, UVa 7/27/01 L2 Alpha Board Commissioning First Production 2/2 pre-production work 7/24 production came up (~9 months effort UIC/UM/FNAL) –Most: multiple vias fixed and a BGA replaced –17 abandoned Broken CIA BGA not replaceable (center of board) –DMA patches (wires, pin lifting) performed –PIO to Alpha not working (firmware) Aug/Sept concentrate on 1 Alpha/crate Today’s score 6 up; 3 down (2 in ICU) But 2 are pre-pro! 6/7 “good” production boards are fragile

3 Bob Hirosky, UVa 7/27/01 L2 Alpha Board Commissioning Second Production ( 2 samples ): DMA fixes incorporated in layout Moved CIA BGA to a socket –Risky, but can’t replace this BGA if it fails new supplier for raw boards better assembly (failures diagnosed; site visits) –DØ pre-production at FNAL – no prompt –UM board up/down CIA SOCKET PROBLEMS –11 to follow: earliest mid-September Probable decision: Drop socket, risk Mounting CIA

4 Bob Hirosky, UVa 7/27/01 I !like Ike!

5 Bob Hirosky, UVa 7/27/01 How many Alphas? 15 + test stand in 2001 Need 15 for nominal system (+7 for test stand) Min. Commissioning ~ 9 boards

6 Bob Hirosky, UVa 7/27/01 Where do we put our Alphas? Staging; rotating tests Aug-Sept (6 to 10  s) 1 Maryland 2 Test Stand/UIC 2 Global 2 Mu/Cal (turns?) 3 in dry dock Oct (6 to20  s ) l 2 Test stand l 2 Global l 2-4 Mu l 2-4 Cal l 2-5 CTT,PS l 1-4 UIC/Test Stand

7 Bob Hirosky, UVa 7/27/01 Online Software ( & to do) Alpha: –Much of structural software exists in simulation Control/data flow for preprocessor and global –Loader and modified Linux kernel –Hardware drivers in EBSDK / Linux –Draft drivers/setup for MBT and event loop testing Some alpha firmware problems? SCL_INIT, and DAQ interface –VME driver, buffer allocation VBD/L3 readout works at test stand; need real SCL/MCH –Error logging and beginnings of monitoring: testing –Downloading, release to Worker –Admin/Worker control; data flow Due to dearth of Alphas, concentrate on 1-alpha crate

8 Bob Hirosky, UVa 7/27/01 Not all bad news: Alphas supplies are tight, but the system is coming together Online software is a big job and we have dug up enough boards to allow progress in this area.

9 Bob Hirosky, UVa 7/27/01 DMA/ PIO ECL drivers 500 MHz  SBC VME Interface L2 Alpha Board Biggest difficulties in SBC section of board Mfg. Problems Obsolete parts Debugging difficulty  Separate SBC and IO

10 Bob Hirosky, UVa 7/27/01 Initially proposed Oct 2000 Baden/Hirosky -Minimize exposure to SBC difficulties -Remove dependence on short lifetime products -Maintain compatibility w/ Alpha

11 Bob Hirosky, UVa 7/27/01 L2  eta people: Bob Hirosky: UVa (Management, specs., device software Alpha transparency) Pierre Petroff, Philippe Cros, Bernard Lavigne: ORSAY (Management, engineering, 9U board production, prototype$) Drew Baden: UMD (Functional reqs., 1 st round designs) Initially proposed Oct 2000 Baden/Hirosky -Minimize exposure to SBC difficulties -Remove dependence on short lifetime products -Maintain compatibility w/ Alpha L2  eta “group” formed in Jan 2001

12 Bob Hirosky, UVa 7/27/01 6U board Compact PCI 9U board 64 bit <2MHz VME FPGA ECL Drivers 128 bits ~20 MHz MBus 32 bits 66MHz (max) Local bus 64 bits 33 MHz PCI J1 J2 J3 J5 J4 PLX 9656 UII Drivers Clk(s)/ roms PIII Compact PCI card 9U card with “custom” devices (3 BGA’s) –Universe Chip VME interface –commercial 64-bit PCI interface chip –MBus and other logic in FPGA Basic Idea

13 Bob Hirosky, UVa 7/27/01 SBC Single/Dual PIII up to 933MHz 64-bit, 66MHz PCI Mech. shock tolerance 50g for transit (immune to ‘Eisenhower effect’?)

14 Bob Hirosky, UVa 7/27/01 6U board Compact PCI 9U board 64 bit <2MHz VME FPGA ECL Drivers 128 bits ~20 MHz MBus 32 bits 66MHz (max) Local bus 64 bits 33 MHz PCI J1 J2 J3 J5 J4 PLX 9656 UII Drivers Clk(s)/ roms IDE Mechanical view of a L2  eta processor SPY

15 Bob Hirosky, UVa 7/27/01 3x CPU performance + >2x on chip cache DMA BIST Additional P2 I/O pins available (~8) More control in interrupt/reset logic CPU/MHzSpecint95Specfp95 Alpha/500~15~21 PIII/850~41~35 PIII/933~45~39 I/O Performance Alpha~100 MB/s MBT~160 MB/s L2  eta ~200 MB/s SBC~500 MB/s New/Improved features: Cheap upgrade = add 2 nd CPU

16 Bob Hirosky, UVa 7/27/01 Linux -software compatibility! -programmer conservation PLX CFG ROM Xilinx FPGA/Veralog

17 Bob Hirosky, UVa 7/27/01 Schematics delivered July 24 Layout starts now Full mechanical designs in September Fulltime firmware development starts September

18 Bob Hirosky, UVa 7/27/01 Production/Assembly Assembly by Thomson (Thales) of France produce PCB (subcontract) assemble components component acquisition under study design/manufacture of mechanical components rails for 6U card stiffeners for 9U card front panel (ORSAY design) (Mech. drawings in early September) electrical testing (JTAG scans) Xilinx / PLX / UII support interface

19 Bob Hirosky, UVa 7/27/01 Cost to build L2  eta system 9U PCB + Mech.$1200 9U Components$1050 9U Assembly$200 9U Total$2450 SBC$3000 Production prototypes (2) $12, boards~$165,000 ~$5450/board

20 Bob Hirosky, UVa 7/27/01 Schematics - Now Layout – October 2001 Device driver API – November 2001 Firmware – December 2001 Prototypes – December 2001 Hardware Integration – Feb 2002 System Integration - March 2002 Begin production – March 2002 Schedule L2beta web site from L2  HARDWARE page or


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