1. This file contains a block diagram and some functional notes on the L2Beta 9U card design. Results of discussions among Philippe Cros, Drew Baden, and Bob Hirosky are merged into the design. Base design uses an Altera 20K200 FPGA and PLX 9054 PCI interface The choice of the Altera will expedite our firmware development cycle. The choice of the PLX chip will give our design greater flexibility, because the PLX supports both 3.3V and 5V PCI buses. Use of a commercial PCI interface will also reduce our firmware complexity. Details of the mechanical design are show in talks by Philippe Cros.

2. PLX ADDON P1 P2 ALTERA 20K200 360 (of 272) pins used TTL 2 PECL VME Block Config/Spy Block MB Arb. Block LBus Block FIFO Block Scaler Block FIFO (18bits x4k)x8 MB AD/DA Block AD dir DA enables Overview of FPGA Blocks MBAD MBDA MB_PECL MB TTL 62 15 32 36 TSI MBus Block 23 14 163 15 These blocks have tightly coupled functions P3

3. Add-on bus DQ[31:0] 62 signals BP_CLK IRQ* SYSRST* ADR[6:2] BE[3:0]* SELECT* WR* RD* PT_NUM[1:0] PTBE[3:0]* PTATN* PTBURST* PTADR* PTWR PTRDY* WRFULL WRFIFO* RDEMPTY RDFIFO* Add-on bus block Fixed by AMCC SPECS

4. VME block P1 GAP* GA[4:0]* 6 signals P2 SCL_INT/Worker_int L2 Answer Ready 9 signals VBD_DONE VBD_Start_Request/VBD_START J2_Test_Out(0)/Worker1_Int J2_Test_Out(1)/Worker2_Int Worker3_Int Worker4_Int Worker5_Int Clock Reset 36 signals EPROM[5] JTAG[5]? Logic Analyzer[16] Switches[4] LED DISPLAY[4]? Config./SPY block JTAG/EPROM/DIAGNOSTIC I/O, etc

5. MOD_DONE[15] EV_LOADED[3] START_LOAD DONE_OUT MB_RESET AP_FIFO_EMPTY 55 signals ECL SALERS[32] TSI MBus+scalar block “MISC” out: EV_LOADED[3:0], START_LOAD, DONE_OUT, MB_RESET, AP_FIFO_EMPTY VME block (signals on P1&P2) P1 GA[5:0]* 6 signals P2 SCL_INT/Worker_int L2 Answer Ready 9 signals VBD_DONE VBD_Start_Request/VBD_START J2_Test_Out(0)/Worker1_Int J2_Test_Out(1)/Worker2_Int Worker3_Int Worker4_Int Worker5_Int

6. Mbus Arbitration MB_WR* 14 signals DDONE* Open collector MBUS arbitration lines require output buffers and separate input pins DSTROBE*BOSSREQ*BOSSBROUT*BOSSGRIN*BOSS* TTL 2 PECL P3

7. MBUS AD/DA + FIFO block OE PIO_OUT OE PIO_IN AD_DIR AD[32] WCLK, WEN RCLK,REN,OE EF,FF FIFO (18bits x4k)x8 DA[128] FPGA 188 Pins used P3 MB DMA AD[10]

8. BROADCAST DATA IN FIFO WEN set (PIO OEs deasserted) by address decode FIFO WCLK = WEN + DSTROBE (New address sets FIFO_IN bits to flag BOE) PIO DATA IN (TARGET MODE) OE_PIO_IN set (OE_PIO_OUT, FIFO_OE deasserted AD_DIR=0) by address decode Data/Address latched in FPGA at DSTROBE, DDONE pulsed PIO DATA OUT (TARGET MODE) OE_PIO_OUT set (OE_PIO_IN, FIFO_OE deasserted, AD_DIR=0) by address decode Address latched in FPGA on DSTROBE/RW DATA fetched, placed on MBUS, DDONE pulsed PIO DATA OUT (MASTER MODE) Boss Requested OE_PIO_OUT set (OE_PIO_IN, FIFO_OE deasserted, AD_DIR=1) AD/DATA placed on MBUS, WR set, DSTROBE pulsed DDONE received, OE_PIO_OUT deasserted, AD_DIR=0 PIO DATA IN (MASTER MODE) Boss Requested OE_PIO_IN set (OE_PIO_OUT, FIFO_OE deasserted, AD_DIR=1) ADDR placed on MBUS, WR set, DSTROBE set DDONE received, Data Latched in FPGA, OE_PIO_IN&DSTROBE deasserted,AD_DIR=0 DEFAULT settings: AD_DIR = 0 (input mode) PIO_OE_IN=PIO_OE_OUT=FIFO_OE=0 Arbitration of shared inputs from Mbus to FPGA

9. Comments: Explicit CDF compatibility is not implemented in this draft The FIFO outputs share the same FPGA I/O pins as PIO, FIFO readout is simplified, because it’s done in 128 bit words Spare bits in the FIFO’s are used to tag beginning and possibly end of a data source, this can simplify DMA firmware Utility features include LA hookups to FPGA, LEDS, and switches 16 free I/O pins are still available in this configuration, additional pins could easily be made available by: Adding external logic to MBUS Arbitration (~5) Reducing FIFO special bits (~2) Reducing LA/LED/Switch bits (~10) POSSIBLE FREE PINS w/ minimal impact on design ~ 33 Uses for additional I/O pins (and pins needed for each function): Provide compatibility w/ a custom designed 64-bit interface (~12-16 pins) Provide compatibility w/ a 64-bit PCI local bus (~40 pins) (Possible at expense of LA pins at time of upgrade – Firmware redefinition) Provide compatibility w/ CDF J2 signals (~37 pins) Address FIFO (~10 pins plus support logic) (Maybe possible at expense of LA pins, LEDS, switches AND 64 bit upgrade option) More LA hookups, bells, whistles, etc…

10. Additional Comments: More pins may be freed up by using 32 bits to ECL drives as LA bits. A front panel redefine these line to be LA lines, instead of scalar lines for diagnostic testing. This would leave us with more than 40 free I/O pins in the design proposed here.