1. Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev. 2009 AGATA PROJECT PREPROCESSING MEZZANINE SLOW CONTROL GUI FOR THE SEGMENT AND THE CORE CARD By : N. Karkour and S. Perrier

2. Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev. 2009 PC Keyboard User’s PC GUI Server ENX Driver Linux Driver B_RAM FPGA Mezzanine VHDL CODE SOAP

3. Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev. 2009 Add a register Erase a register Change a connection parameter Home page and card selection Core CardSegment Card EPROM Data read for the Data base. All the registersEnergyTraceCommon registermanual Mode login Page Card selection and connection configuration Parameters

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20. Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev. 2009 Why this slow control is not implemented The cards prototype and preseries validation was delayed (due to several reasons that is known by the whole community). The lack of manpower to define and design the slow control specification (lower priority) The PPC interface for the Virtex4 VHDL developpement started in September 2008. Status is pb. With the ethernet interface with the carrier card switch. Xilinx opb ethernet driver is not supported for Linux 2.6. Must used ethernet lite or LLTMAC The PPC interface for the Virtex 2 pro developpement could not be used for the new rework due to the difficulties encountered due to the Xilinx Development tools version upgrades from 8.2 to 10.1. Mezzanine Flash memory uses a Nand technology. Advantage: small SMD with few I/O control lines (20 I/O for 256 Mbytes).

21. Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev. 2009 Why this slow control is not implemented This flash is used to house the Linux Operating system. The Inconvenience : No Xilinx Driver to integrate under EDK tool like the Strata flash. Strata flash cannot fit on the mezzanine pcb. New flash driver interface is needed to simulate Strata flash simulation Driver to be designed completely from scratch (started in mid January 2009).. Hope that VHDL code implementation only is sufficient. Worst case is to re-develop all the Programming steps that Xilinx EDK tool to load the Linux operating system. Status: single read/write and erase operation is under test. Futur work is to insert a strata flash into the EDK project and verify that Linux boot loader is OK. Hope to be ready for Agata week in April

22. Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev. 2009 What slow control is actually implemented I2C basic slow control for the Triple cluster tests is developped by Padoue. Contains only necessary parameters for the Data transmision and collection. Can be used to check Hardware, validate prototypes and preseries. Write only registers. No read back values Must exist to qualify TC tests. Can be used for the Demonstrator to validate data transmission ONLY. MUST NOT be used for the demonstrator because it is not for physicists. No diagnostics, No spy on data stream. No test mode. Setup is done automatically by script. Difficult to change parameter values by hand. Must use keyboard commands through telnet interface. (not suitable for user defined). Thanks for Padoue’s engineers for this good job.

23. Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev. 2009 Replace the I2C interface to reduce the actual EDK projects (5 in parallel). Implement the PPC interface to start using the actual GUI. Add temperature measurements to send to crate controller (crucial for full crates). Components temperature can reach 60° in < 1 min if fans are off. ALL mezzanines MUST send temperature readout through PPC and to the crate manager to decide if the crate power supply must turn off. Increase parameters setup ( self test, R I/O transceiver tests etc.) Enhance GUI and slow control for the physicist user to be able to run, modify and monitor experiments and analyse data quality online. MUST exist for the demonstrator and NOT wait for the Next phase. MUST exist in 2009 Short term work to be implemented

24. Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev. 2009 More parameter setup( test mode, RG transceiver tests) Diagnostic parameters during experiments run Maybe merge diagnostics with DAQ data to trace defected channels. Replace scope monitoring for experiment calibration and continuous statistics Integrate act on all channels segments and detectors buttons (not yet designed and thought of) Integrate local statistics with global statistics. Integrate individual data to identify each detectors specific aspects (homogeneity, symmetry or special coefficients specific for each detector. Integrate spy data with experiment data. Compare PPC processing with DAQ processing. Future characteristics to be implemented (need discussion urgently)