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Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-1 Chap. 5 Flip-Flops and Related Devices n Introduction Combinational Circuit l The output levels at any instant of time are dependent on the levels present at the inputs at that time »Any prior input-level conditions have no effect on the present outputs because combinational logic circuits have no memory Most Digital Systems = Combinational circuits + Memory elements l General digital system that combines combinational logic gates with memory device : Fig. 5-1 »The external outputs are a function of both its external inputs and the information stored in its memory elements The most important memory element = Flip-Flop l F/F is made up of an assembly of logic gates »Even though a logic gate, by itself, has no storage capability, several can be connected together in ways that permit information to be stored Output State of F/F : Fig. 5-2 l Normal output (Q) : 0 or 1 1 = HIGH = Set l Inverted output(Q) : 1 or 0 0 = LOW = Clear = RESET F/F = Latch = Bistable multivibrator
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-2 n 5-1 NAND Gate Latch NAND gate latch(or Latch) l Constructed from two NAND gates : Fig. 5-3 Setting the Latch l Both cases Q ends up HIGH : Fig. 5-4 Clearing the Latch l Both cases Q ends up LOW : Fig. 5-5 Simultaneous Setting and Clearing l Set = Clear = 0 »Q = = 1 : Undesired condition l Set = Clear = 1 »No change Summary l Truth table : Fig. 5-6(b) Fig possible resting state when SET=RESET= Q Fig. 5-4 Pulsing SET input to 0 Fig. 5-5 Pulsing CLEAR input to 0 Fig. 5-3 참고
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-3 Alternate Representations : Fig. 5-7 Ex. 5-1) Determine Q output in Fig. 5-8 Ex. 5-2) Switch debouncing circuit in Fig. 5-9 n 5-2 NOR gate Latch Ex. 5-3) Determine Q output in Fig Ex. 5-4) what happen if the light beam is momentarily interrupted in Fig l Q will remain HIGH and the alarm will remain ON even if phototransistor return to ON( Set=0, Clear=0 : no change) F/F State on Power-Up l When power is on, not possible to predict the starting state of a F/F’s output l Output depend on factors such as internal propagation delays, parasitic capacitance, and external loading Fig. 5-7 Alternate Representation Resting Input = 0 * Invalid Q = = 0 Q Fig (a) NOR gate latch, (b) truth table, (c) simplified block symbol * Inactive Stage(Resting ) NAND latch : S=C=1 NOR latch : S=C=0
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-4 n 5-3 Troubleshooting Case Study Ex. 5-5) Describe & analyze the circuit in Fig Ex. 5-4) what are the possible faults(refer to Tab. 5-1 ) l Possible faults(Switch position A 에서 Q=1 이여야 함 ) »Internal open at Z1-1 : 0 이 입력되지 않음 »Component failure in NAND gate Z1 »Internally shorted to ground at Z1-3, Z1-4, and Z2-2 n 5-4 Clock Signals and Clocked F/Fs Async/Synchronous System l Asynchronous System : The output of logic circuits can change state any time one or more of the input change l Synchronous System : The exact times at which any output can change states are determined by a signal commonly called the clock »Synchronous circuits are easier to design and troubleshoot because the circuit outputs can change only at specific instants of time. Clock Signal = rectangular pulse train or square wave ( Fig ) l Positive-Going Transition(PGT), Negative-Going Transition(NGT) l The synchronizing action of the clock signals is accomplished through the use of clocked flip-flops
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-5 Clocked Flip-Flops : Fig l 1. Clocked FFs have a clock input(CLK, CK, or CP) »In most clocked FFs, the CLK input is edge-triggered : NGT or PGT l 2. Clocked FFs have one or more control inputs »The control inputs will have no effect on Q until the active clock transition occurs(=Synchronous control inputs) l 3. In summary, »The control inputs control the WHAT : Output state(DATA 0 or 1) will go to »The clock input determines the WHEN : actually triggers the change Setup and Hold Times l Setup time( ns) »minimum time that control input must remain at constant value before the transition. l Hold time( ns) »minimum time that control input must not change after the positive transition n 5-5 Clocked S-C F/F Clocked S-C F/F l Waveform analysis in Fig : positive going edge transition t s t h Positive clock transition Control Input Clock Input Set-Clear F/F 50 %
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-6 l The clock input = Trigger input l Negative-going edge transition : Fig Internal circuitry of the edge-triggered S-C F/F l Edge-triggered S-C F/F : Fig »1. NAND Latch »2. Pulse-steering : NAND gate 에 모두 1 이 입력되면 SET=0 이 되고 Q=1 »3. Edge-detector : Fig n 5-6 Clocked J-K F/F Clocked J-K F/F : Fig l Toggle Mode : J = K = 1(S-C F/F 에서는 Invalid) l Negative-going edge transition : Fig Internal circuitry of the edge-triggered J-K F/F : Fig l Q=0, = 1 인 상태에서 J=K=1 이 입력되면 »NAND 1 의 입력은 모두 1 이고 따라서 출력은 0 이 되고 Q =1 로 Toggle »NAND 2 의 입력은 1, 1, 0 이고 따라서 출력은 1 이 되고 =0 으로 Toggle n 5-7 Clocked D F/F Clocked D F/F : Fig Parallel Data Transfer : Fig Implementation of the D F/F : Fig. 5-25, 26 Q Q Jack-King F/F Data F/F
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-7 n 5-8 D Latch : Transparent Latch D Latch : Fig l Edge detector is not used : EN(Enable) input 사용 Ex. 5-8) Determine waveform Q in Fig n 5-9 Asynchronous Inputs Asynchronous Inputs(= override inputs) l Used to set the FF to the 1 or clear the FF to the 0 state at any time, regardless of the conditions at the other inputs l Clocked J-K F/F with asynchronous inputs : Fig Designations for Asynchronous Inputs l PRE(Preset), CLR(Clear) l S D (Direct SET), R D (Direct RESET) Ex. 5-8) Determine the Q output in Fig n 5-11 F/F Timing Considerations Setup/Hold Time Propagation Delays : Fig ( Typ. MAX Few ns ) l t PLH : Delay going from LOW to HIGH, t PHL : HIGH to LOW D Latch is not edge Triggered, (Level Triggered) Use the overbar to indicate the active LOW CLK Q t PHL t PLH
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-8 Maximum Clock Frequency : f MAX ( Typ. Max 20 to 35 MHz ) Clock Pulse HIGH and LOW Times : Fig. 5-36(a) l The minimum time duration that the CLK must remain LOW before it goes HIGH t W (L), and HIGH before it returns LOW t W (H) Asynchronous Active Pulse Width : Fig. 5-36(b) l The minimum time duration that a PRESET or CLEAR input must be kept in its active state in order to reliably set or clear the FF l t W (L) for active-LOW asynchronous inputs Clock Transition Times l Manufacturer usually do not list a maximum transition time requirement l Generally less than 50 ns for TTL, and less than 200 ns for CMOS Actual ICs : Tab. 5-2 (TTL : 7474, 74LS112, CMOS : 74C74, 74HC112) Ex. 5-10) Determine following from Tab. 5-2 l (a) t PLH = 25 ns for 7474, (b) t PHL = 41 ns for 74HC112, (c) t W (L) for 74LS112, active-LOW CLR input, (d) 7474, Hold time is needed(non-zero hold time), (e) All F/F, Setup time is needed(No non-zero setup time) CLK
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-9 n 5-12 Potential Timing Problem in FF Circuits Potential Timing Problem : Fig l J2 input of Q2 will be changing as it receives the same NGT( ). This could lead to an unpredictable response at Q2 해결책 : t PHL must be greater than Q2’s hold time requirement l Hold time 이 적다 = CLK 후에도 control input 을 계속 유지시킬 필요 없음 l Fortunately, all modern edge-triggered FFs have hold time requirements that are 5 ns or less; most have t H = 0(clock transition 과 동시에 control input 이 바뀌어도 상관이 없다 ) l For these FFs, situation like that in Fig will not be a problem 가정 : FF’s hold time requirement is short enough to respond reliably l The FF output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition »if we apply this rule to Fig. 5-37, J2 = 1, K2 = 0 Ex. 5-11) Determine the Q output in Fig l Clock transition 의 이전 입력 값을 갖는다 CLK 입력과 동시에 J2 에는 1(Q1) 이 유지되어야 하지만 J1 = K1 = 1 에 따라 Toggle 되어 CLK 입력과 동시에 곧바로 J2 = 0 이 되어 J2 의 Hold time 을 만족 시킬 수 없다 - 현재 그림은 정상 동작 - CLK 입력 전에 Q1 = 1 이며, CLK 입력과 동시에 J2 = 1 이고 따라서 Q2 = 1
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-10 n 5-13 Master/Slave FFs Master/Slave FF l 2 개의 F/F 을 사용 (Slave 와 Master F/F) 하며 negative-edge transition 사용 l 위와 같이 사용하는 이유 : Timing Problem 해결 (Sec 5-12) Timing Problem 의 해결 방법 l Negative Edge triggered F/F : 현재 사용 l Master/Slave F/F 사용 : 과거에 사용 예제 l 7470 : J-K Edge triggered F/F l 7471 : J-K Master/Slave F/F n 5-14 FF Application Unclocked FFs l Switch debouncing(Ex. 5-2), Event storage(Ex. 5-4) Clocked FFs l We will briefly introduce the more common applications in the following sections
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-11 n 5-15 FF Synchronization Asynchronous signal input l A human operator’s actuating input switch at some random time l A FF can be used to synchronize the effect of an asynchronous input l Partial Pulse : Fig »The operator actuates or releases the switch are essentially random, This can produce partial clock pulses at output X l A method for preventing the appearance of partial pulses : Fig n 5-16 Detecting an Input Sequence Detecting an Input Sequence : Fig l An output is to be activated only when the inputs are activated in a certain sequence »HIGH output only if A goes HIGH and then B goes HIGH some time later n 5-17 Data Storage and Transfer Register l A data(binary number, BCD number,..) are generally stored in groups of FFs called registers FF Synchronization
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-12 Data Transfer l The data transfer involves the transfer of data from one FF or register to another l The logic value stored in FF A is transferred to FF B upon the NGT of the TRANSFER pulse l Synchronous data transfer : Fig l Asynchronous data transfer : Fig »Transfer Enable = 0 : PRE=CLR=1, 통상적인 FF 으로 동작 »Transfer Enable = 1 : A=1 이면 B=1, A=0 이면 B=0 Parallel Data Transfer : Fig l The contents of X1, X2, and X3 are transferred simultaneously into Y1, Y2, and Y3(Upon application of the PGT of the TRANSFER pulse) l Parallel transfer does not change the contents of source register n 5-18 Serial Data Transfer : Shift Registers Shift Register : Fig l A group of FFs arranged so that the binary numbers stored in the FFs are shifted from one FF to the next for every clock pulse Hold Time Requirement l In shift register, the FFs must have a very small or zero hold time requirement Sec Timing Problem 과 동일
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-13 Serial Transfer between Registers : Fig Ex. 5-13) The contents of each FF after sixth shift pulse in Fig ? l The registers are filled up with zeros(zero inserted) Shift-Left Operation l 역으로 배치 (Shift 방향에 따른 장단점은 없으며, 응용 특성에 따라 선택 ) Parallel versus Serial Transfer l Parallel transfer : Speed »All of the information is transferred simultaneously upon the occurrence of a single transfer command pulse l Serial transfer : economy and simplicity »The complete transfer of N bits requires N clock pulses n 5-19 Frequency Division and Counting 3 bit binary counter : Fig l The FFs change state(toggle) whenever the pulses are applied l Each FF divides the frequency of its input by 2 Counting Operation : Fig. 5-48(State Table) State Transition Diagram : Fig l Graphical representation of state table »Circle(state), Line(transition), I/O(input/output) 여러 개의 Transmission wire 필요 N 개 FF 은 1/2 N 까지 분주 가능 /0 clock
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-14 MOD Number l MOD Number indicates the number of states »N Flip-flops = 2 N different state, and count up to 2 N - 1 Ex. 5-14) What will be the state after 13 pulses( 현재는 101) in Fig Ex. 5-15) 6 Flip-flop arrangement of Fig n 5-20 Microcomputer Application Transfer binary data of internal register to external register X : Fig l 1) Place the binary number onto its data output lines l 2) Place the proper address code on its address output lines l 3) Generate the clock pulse CP(Write signal) Ex. 5-16) a) What is address decode logic ? : b) address code = 일 때 X = ? : X will not change( 그대로 0110) n 5-21 Schmitt-Trigger Devices Schmitt-Trigger Inverter : Fig l Schmitt-trigger type of input is designed to accept slow-change signals and produce an oscillation- free output STATE 1 0 V T- V T+ VOLT
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-15 보통 “0” 에서 “1” One-Shot tp tp Quasi-stable State n 5-22 One-Shot(=Monostable Multivibrator) One-Shot : Fig. 5-52(a) l 1) Once triggered by trigger input(T), Q = Opposite state l 2) “1” remains for a fixed period of time t p (Determined by t p = 0.69RC) l 3) After a time t p, the OS outputs return to their resting state(“0”) Non-retriggerable One-Shot : Fig. 5-52(b) Retriggerable One-Shot : Fig Actual Devices : Fig l 74121/221 : Single/Dual non-retriggerable one-shot l 74122/123 : Single/Dual retriggerable one-shot n 5-23 Analyzing Sequential Circuits Analyze a sequential circuits( FFs + Gates ) in the following example Ex. 5-17) Determine the waveform at X, Y, Z, and W for 8 clock cycles l Counter stops counting at X=1, Y=0, and Z=0(W=0 : no change)
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-16 n 5-24 Clock Generator Circuits Multivibrator l Bi-stable multivibrator : Flip-flops have two stable state l Mono-stable multivibrator : One-shots have one stable state(“0”) l Astable = Free-running multivibrator : no stable state Schmitt-Trigger Oscillator : Fig 555 Timer Used as an Astable Multivibrator : Fig Ex. 5-17) Calculate the frequency and the duty cycle of the 555 timer Crystal-Controlled Clock Generators l Output frequency = Crystal’s resonant frequency l Clock Generator Circuit : Fig »Using TTL inverter : R = Ohm, 최대 20 MHz »Using CMOS inverter : R = 100 K Ohm, 최대 10 MHz n 5-25 Troubleshooting FF circuits Open Inputs : Ex l K 0 가 Open 되어 J 0 = K 0 = 1 로 Toggle 됨 (TTL open = 1) “1” = Quasi-Stable State * R depends on the type of crystal used and its frequency(Graph 로 제공됨 )
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-17 Shorted Outputs : Ex l D(Z2-2) 에 0 이 입력되며, 따라서 Q(Z2-5) = 0 이어야 정상 l Possible Circuit Faults »Z2-5 or Z1-4 is internally shorted to Vcc »Z2-5 or Z1-4 is externally shorted to Vcc »Z2-4 is internally or externally shorted to GROUND(Preset : Q = 1) »Z2 internal failure l In case of Z2 internal failure »1) Check Z2’s Vcc and GROUND : O.K. »2) Unsoler Z2, and Check it’s amplitude, frequency, pulse width, and transition times (by using oscilloscope) : O.K. »3) Replace it with new one, but the new chip behaves in exactly the same way »4) Finally he detects a solder bridge between pins 6 and 7 of Z2 »5) Remove the solder bridge and then the circuit functions correctly l Explain how this fault produced the operation observed »The Q and outputs are internally cross-coupled so that the level on one will affect the other »A constant LOW at would keep a LOW at one input of NAND gate so that Q would have to stay HIGH regardless of the J or K 현재는 Q = 1 Rule out Q Q “1” “0” Both outputs should be checked for faults, even those that are not connected to other devices
Digital Systems © Korea Univ.. of Tech. & Edu. Dept. of Info. & Comm. Chap. 5 Flip-Flops and Related Devices 5-18 Clock Skew l A clock signal arrives at the CLK inputs of different FFs at different times(propagation delay 가 원인 ) l The skew can cause a FF to go to a wrong state : Fig »Q2 는 CLOCK 1 에서 Q1=0 이 입력되어 계속 Q2=0 이 되어야 함 ( 그러나 그림에서는 CLOCK 2 이후에 Q2=1 이 되어 오동작 ) l 해결 방법 »Problems caused by clock skew can be eliminated by equalizing the delays(the active transition arrives at each FF at approximately the same time) 각각의 Clock Input 에서의 Propagation Delay 를 계산
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