Download presentation

Presentation is loading. Please wait.

Published byCael Thackery Modified over 3 years ago

1
CSIS 3510 Computer Organization and Architecture Topics covered in this lecture: –Review of De’Morgan’s Theorem –Using De’Morgan’s Theorem –Building a 2-bit decoder –Algebraic Reduction of Boolean Expressions –7-segment decoder

2
De’Morgan’s Theorem On of the most useful principles in boolean algebra is De’Morgan’s Theorem, which allows one to switch between ANDs and NORs and ORs and NANDs. Remember, we want to design circuits using AND and OR, but then implement them using NAND and NOR (AND transistor bleed- through problem, and manufacturing layering minimization) NOT terms or Inverted terms are represented with a line over the terms AB = A + B A + B = AB We demonstrated the validity of DeMorgan’s by Perfect Induction, using a truth table.

3
Using De’Morgan’s Theorem To convert A+B into a form that can be implemented using a NAND gate follow these steps: 1. Double Complement the term A+B = A+B 2. Use DeMorgan’s to distribute one of the complements A+B = A B The equation is now a NAND of the complemented inputs. To convert AB into a form that can be implemented using a NOR gate follow these steps: 1. Double Complement the term AB = AB 2. Use DeMorgan’s to distribute one of the complements AB = A + B The equation is now a NOR of the complemented inputs.

4
Extracting a function from a truth table and converting ABOutput 000 011 100Out = A B 110DoubleC A B DeM A + B Simplify A + B

5
Two-Bit Decoder ABF0F1F2F3001000010100100010110001ABF0F1F2F3001000010100100010110001 F 0 = A B = A B = A+B = A+B F 1 = A B = A B = A+B = A+B F 2 = A B = A B = A+B = A+B F 3 = A B = A B = A+B

6
Two-Bit Decoder Diagram A A B B F0 F1 F2 F3

7
Algebraic Reduction of Boolean Functions Algebraic reduction is used to minimize a function extracted from a truth table or other source. Principle is to look for terms where a single variable is present in both complemented and positive form. Those variables can be deleted from those terms. Note: terms can be used over in multiple minimizations. Examples A B + A B = B,A B + A B = A A B C + A B C = A B A B C + A B C + A B C + A B C A B A B A

8
7-Segment Display Decoder 7 Segment Display: Displaying 0, 1, 2, 3 0 1 2 3 4 5 6

9
7-Segment Display Truth Table (Displaying values from 0-3 only) AB F0 F1 F2 F3 F4 F5 F6 00 1 1 1 1 1 1 0 01 0 1 1 0 0 0 0 10 1 1 0 1 1 0 1 11 1 1 1 1 0 0 1

10
Extracting and Minimizing Segment Functions F0 = F1 = F2 = F3 = F4 = F5 = F6 =

11
Extracting and Minimizing Segment Functions F0 = F1 = F2 = F3 = F4 = F5 = F6 =

12
Extracting and Minimizing Segment Functions F0 = F1 = F2 = F3 = F4 = F5 = F6 =

13
7-Segment Display Decoder Diagram

14
Conclusion Topics covered in this lecture: –Review of De’Morgan’s Theorem –Using De’Morgan’s Theorem –Building a 2-bit decoder –Algebraic Reduction –7-segment decoder Questions?

Similar presentations

Presentation is loading. Please wait....

OK

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures

© 2018 SlidePlayer.com Inc.

All rights reserved.

To ensure the functioning of the site, we use **cookies**. We share information about your activities on the site with our partners and Google partners: social networks and companies engaged in advertising and web analytics. For more information, see the Privacy Policy and Google Privacy & Terms.
Your consent to our cookies if you continue to use this website.

Ads by Google

Ppt on urbanization and environment Ppt on biological pest control Ppt on total parenteral nutrition Ppt on famous business personalities of india Ppt on seasons for kindergarten Ppt on review writing resources Ppt on conceptual article Upload and view ppt online shopping Ppt on seasons in hindi Ppt on history of olympics logo