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CSIS 3510 Computer Organization and Architecture Topics covered in this lecture: –Review of De’Morgan’s Theorem –Using De’Morgan’s Theorem –Building a 2-bit decoder –Algebraic Reduction of Boolean Expressions –7-segment decoder

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De’Morgan’s Theorem On of the most useful principles in boolean algebra is De’Morgan’s Theorem, which allows one to switch between ANDs and NORs and ORs and NANDs. Remember, we want to design circuits using AND and OR, but then implement them using NAND and NOR (AND transistor bleed- through problem, and manufacturing layering minimization) NOT terms or Inverted terms are represented with a line over the terms AB = A + B A + B = AB We demonstrated the validity of DeMorgan’s by Perfect Induction, using a truth table.

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Using De’Morgan’s Theorem To convert A+B into a form that can be implemented using a NAND gate follow these steps: 1. Double Complement the term A+B = A+B 2. Use DeMorgan’s to distribute one of the complements A+B = A B The equation is now a NAND of the complemented inputs. To convert AB into a form that can be implemented using a NOR gate follow these steps: 1. Double Complement the term AB = AB 2. Use DeMorgan’s to distribute one of the complements AB = A + B The equation is now a NOR of the complemented inputs.

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Extracting a function from a truth table and converting ABOutput 000 011 100Out = A B 110DoubleC A B DeM A + B Simplify A + B

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Two-Bit Decoder ABF0F1F2F3001000010100100010110001ABF0F1F2F3001000010100100010110001 F 0 = A B = A B = A+B = A+B F 1 = A B = A B = A+B = A+B F 2 = A B = A B = A+B = A+B F 3 = A B = A B = A+B

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Two-Bit Decoder Diagram A A B B F0 F1 F2 F3

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Algebraic Reduction of Boolean Functions Algebraic reduction is used to minimize a function extracted from a truth table or other source. Principle is to look for terms where a single variable is present in both complemented and positive form. Those variables can be deleted from those terms. Note: terms can be used over in multiple minimizations. Examples A B + A B = B,A B + A B = A A B C + A B C = A B A B C + A B C + A B C + A B C A B A B A

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7-Segment Display Decoder 7 Segment Display: Displaying 0, 1, 2, 3 0 1 2 3 4 5 6

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7-Segment Display Truth Table (Displaying values from 0-3 only) AB F0 F1 F2 F3 F4 F5 F6 00 1 1 1 1 1 1 0 01 0 1 1 0 0 0 0 10 1 1 0 1 1 0 1 11 1 1 1 1 0 0 1

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Extracting and Minimizing Segment Functions F0 = F1 = F2 = F3 = F4 = F5 = F6 =

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Extracting and Minimizing Segment Functions F0 = F1 = F2 = F3 = F4 = F5 = F6 =

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Extracting and Minimizing Segment Functions F0 = F1 = F2 = F3 = F4 = F5 = F6 =

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7-Segment Display Decoder Diagram

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Conclusion Topics covered in this lecture: –Review of De’Morgan’s Theorem –Using De’Morgan’s Theorem –Building a 2-bit decoder –Algebraic Reduction –7-segment decoder Questions?

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