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240-334 by Wannarat 240-334 Computer System Design Lecture 2 Instruction Set Architecture.

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Presentation on theme: "240-334 by Wannarat 240-334 Computer System Design Lecture 2 Instruction Set Architecture."— Presentation transcript:

1 by Wannarat Computer System Design Lecture 2 Instruction Set Architecture

2 by Wannarat What’re the component of ISA? Machine Instruction Set Instruction format Nature of the fetch through execute wannarat: machine instruction set :make use of storage cells, formats, and result of fetch/execute, register transfer instruction format : size and meaning of field within instruction the nature of the fetch-execute cycle : things that are done before the operation code is known. wannarat: machine instruction set :make use of storage cells, formats, and result of fetch/execute, register transfer instruction format : size and meaning of field within instruction the nature of the fetch-execute cycle : things that are done before the operation code is known.

3 by Wannarat Varies Programming Model

4 by Wannarat What must an instruction specify? Which Operation is perform? ADDr1,r2,r3 Where to find the operands ADDr1,r2,r3 Place to store the result ADDr1,r2,r3 Location of next instruction

5 by Wannarat Basic ISA Class Accumulator (1 register) 1 addressadd A; acc <= acc + mem[A] 1 + x addressaddxA; acc <= acc + mem[A+x] Stack : 0 addressaddtos <= tos + next General Purpose Register 2 addressaddA, B 3 addressaddA, B, C wannarat: add A, B; A = A + B add A B C; A = B + C wannarat: add A, B; A = A + B add A B C; A = B + C

6 by Wannarat Basic ISA Classes(con’t) Load/Store load Ra, RbRa <= mem[Rb] Store Ra, Rbmem[Rb] <= Ra

7 by Wannarat Compare number of instruction Code Sequence for C = A + B StackAccumulator RegisterRegister (reg. - mem) (load/store) Push ALoad ALoad R1,ALoad R1,A Push BAdd BAdd R1,BLoad R2,B AddStore CStore C, R1Add R3,R1,R2 Pop CStore C,R3

8 by Wannarat CPU Register Stack RegisterArithmetic Register & Address Register

9 by Wannarat General Purpose Register all machines use general purpose registers. Advanced of Registers - faster than memory - easier for compiler to use - hold variables wannarat: easier for compiler to use : (A*B) - (C*D) - (E*F) can do multiplies in any order vs. stack hold variables: memory traffic is reduced (program speed up), code density improves ( register named with fewer bits than memory location) wannarat: easier for compiler to use : (A*B) - (C*D) - (E*F) can do multiplies in any order vs. stack hold variables: memory traffic is reduced (program speed up), code density improves ( register named with fewer bits than memory location)

10 by Wannarat Summary Instruction Set Class Data Movement Instructions - Load - Store Arithmetic and Logic (ALU) Instruction - Add, Sub, Shift … Branch Instructions - Br, Brz, …

11 by Wannarat 3-Address Machine and ISA wannarat: Address of next instruction kept in Processor state register (PC) wannarat: Address of next instruction kept in Processor state register (PC)

12 by Wannarat 2-Address Machine ISA

13 by Wannarat 1-Address Machine and ISA

14 by Wannarat 0-Address Machine and ISA wannarat: Push-down stack in CPU, Arithmetic uses stack for both operands and result, Computer must have 1-address instruction to push and pop operands to and from the stack wannarat: Push-down stack in CPU, Arithmetic uses stack for both operands and result, Computer must have 1-address instruction to push and pop operands to and from the stack

15 by Wannarat Examples a = (b+c)*d - e 3-address 2-address1-address stack add a,b,c load a,bload b push b mpy a,a,d add a,cadd c push c sub a,a,e mpy a,dmpy d add sub a,esub e push d store a mpy push e sub pop a

16 by Wannarat Real Machine Have mixture of 3, 2, 1 or 0 address instructions if ALU instructions only use registers for operands and result, machine type is load-store mix of register-memory and memory-memory

17 by Wannarat Break 5 Minutes

18 by Wannarat Addressing Mode

19 by Wannarat Addressing Mode Addressing ModeExamplesMeaning RegisterAdd r4,r3r4 <= r4 + r3 ImmediateAdd r4,#3r4 <= r4 + 3 Displacement Add r4,100(r1)r4 <= r4 + mem[100+r1] indirect(r)Add r4,(r1)r4 <= r4 + mem[r1] index+base Add r3,(r1+r2)r3 <= r3 + mem[r1+r2] DirectAdd r1,(1001)r1 <= r1 + mem[1001] indirect(m) Add <= r1 + mem[mem[r3]] auto-increAdd r1,(r2)+r1 <= r1+mem[r2];r2=r2+d auto-decreAdd r1,-(r2)r2 <=r2-d,r1<=r1+mem[r2] scaledAdd r1,100(r2)[r3] r1 <=r1+mem[100+r2+r3*d]

20 by Wannarat MIPS Registers 31 x 32-bit GPR (R0 = 0) 32 x 32-bit FP register PC lo hi-multiplier output register R0 R1 R31 PC lo hi

21 by Wannarat Memory Addressing Since 1980, Most machine uses address to level of 8-bits (byte) How do byte address map onto words? Can a word be placed on any byte boundary?

22 by Wannarat Endianess and Alignment Big Endian : 68k, SPARC, MIPS, HP PA Little Endian : 80x86,DEC(Vax, Alpha)

23 by Wannarat Generic of Instruction format width Variable : Fixed: Hybrid :...

24 by Wannarat Summary ISA Variable length instructions, if code size is very important. Fixed length instructions, if performance is most important. Embedded Machine (ARM, MIPS) have optional mode to execute 16-bitwide. (decide performance or density)

25 by Wannarat To be Continuous

26 by Wannarat Part II : Lecture 2

27 by Wannarat MIPS ISA Target Embedded System used by NEC, Nintendo, Silicon Graphics, Sony

28 by Wannarat MIPS ISA

29 by Wannarat MIPS Addressing Modes All instructions have 32-bit wide.

30 by Wannarat MIPS Arithmetic Instruction InstructionExampleMeaning 1.addadd $1,$2,$3$1 = $2 + $3 2.subtractsub $1,$2,$ add immeaddi $1,$2, add unsignaddu $1,$2,$ subu $1,$2,$ addiu $1,$2, multiplymult$2,$3Hi,Lo = $2x$3 8.multu $2,$

31 by Wannarat MIPS Arithmetic Instruction InstructionExampleMeaning 9.dividediv $2,$3Lo=$2/$3, Hi=$2mod$3, 10.Divu $2,$3 11.movmfhi $1 12.mflo $1

32 by Wannarat MIPS Logical Instruction InstructionExampleMeaning 13.ANDand 14.ORor 15.XORxor 16.NORnor 17.andi 18.ori 19.xori 20.shift left logical sll $1,$2,10 21.Srl $1,$2,10

33 by Wannarat MIPS Logical Instruction InstructionExampleMeaning 22.shift right arithm sra $,$2,10 (sign extend) 23.sllv 24.srlv 25.srav

34 by Wannarat MIPS data transfer instructions 26. sw 500(r4),r3Store word 27.sh 502(r4),r3store half word 28. sb 41(r4,r3store byte 29.lw r1,30(r2)load word 30.Lh r1,40(r2)load half word 31.Lb r1,40(r2)load byte 32lui r1,40load upper immediate (16 bits shifted left by 16)

35 by Wannarat Testing Condition Condition Code addr1,r2,r3 bzlabel Condition Register cmpr1,r2,r3 bgtr1,label Compare and Branch bgtr1,r2,label

36 by Wannarat MIPS Compare and Branch Compare and Branch BEQrs,rt,offset BNErs,rt,offset compare to zero and Branch BLEZrs, offset BGTZrs, offset BLT< BGEZ>= BLTZALif R[rs] < 0 then branch and link(to R31) BGEZAL>=

37 by Wannarat MIPS Jump, Branch Compare

38 by Wannarat Software conventions for Register

39 by Wannarat Note for MIPS Instruction Set R0 always = “0” (even if u try to write) Branch/jump and link PC+4 ->R31 Imme arith and logical are extended - logical imme op are zero extend to 32 bits - arith imme op are sign extend to 32 bits data loaded by lb, lh extended - lbu, lhu are zero extended - lb, lh are sign extedned Overflow occur in ADD, SUB, ADDI Don’t occur in ADDU, SUBU, ADDIU, AND, OR, XOR, NOR, SHIFT, MULT, MULTU, DIV, DIVU

40 by Wannarat MIPS arithmetic Instruction has 3 operands Operand order is fixed Pascal Code : a := b + c; MIPS Code :add $s0, $s1, $s2

41 by Wannarat MIPS Arithmetic Pascal Code : a := b + c + d; e := f - a; MIPS Code :add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0

42 by Wannarat Register & Memory Registers were used in Arithmetic Instructions - 32 registers

43 by Wannarat Memory Organization Memory is an index into the array Byte Addressing = points to a byte of memory 1 8 bits of Data

44 by Wannarat Memory Organization For MIPS, a word is 32-bit or 4 bytes 2 32 bytes with byte addresses from 0 to words with byte address from 0, 4, 6, …, bits of Data

45 by Wannarat MIPS Load/Store Instruction Code : A[8] = h + A[8]; A[8] ==> 8 x 4 = 32 (word alignment) MIPS Code :lw $t0, 32($s3); add $t0,$s2,$t0; sw $t0, 32($s3); Arithmetic Operand is Register, not Memory!!

46 by Wannarat Example : Swap (int v[], int k); { Int temp; temp = v[k];swap:muli $2, $5, 4 v[k] = v[k+1];add $2,$4,$2 v[k+1]=temp;lw $15, 0[$2] }lw $16, 4[$2] sw $16, 0[$2] sw $15, 4[$2] jr $31

47 by Wannarat Meaning add$2, $4, $2$2 = $4 + $2; lw$16, 0[$2]$16 = Memory[0 + $2] sw$15, 4[$2]Memory[4+$2] = $15

48 by Wannarat Machine Language Instructions, like register & words of data are 32 bits long. - add $t0, $s1, $s2 - register : $t0 = 9, $s1 = 17, $s2 = 18 Instruction Format

49 by Wannarat Machine Language I-type for Data transfer instruction Example : lw $t0, 32($s2)

50 by Wannarat Control Decision Making instructions MIPS conditional branch instructions: - bne $t0, $t1, label - beq $t0, $t1, label Example : if (i=j) h= i +j; bne$s0, $s1, Label add$s3, $s0, $s1 Label :...

51 by Wannarat Control MIPS unconditional Branch Example : if ( i != j)beq$s4, $s5, label; h=i+j;add$s3, $s4, $s5; elsej lab2 h=i-j;lab1: sub $s3, $s4, $s5 lab2: …

52 by Wannarat Summarize :

53 by Wannarat

54 Homework Use MIPS Assembly to write program. 1. “Factorial Program” n is input, Example : if n=3, result = 3! = 3 x 2 x 1 = 6

55 by Wannarat Homework Use MIPS Assembly to write program. 2. Write program that use Most of the MIPS instructions

56 by Wannarat MIPS Instruction Encoding Please see more detail in the Figure 3.18 Page 153,


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