1. Microprocessor Dr. Rabie A. Ramadan Al-Azhar University Lecture 4

2. Machine Cycles and Bus Timings Microprocessor includes 158 different instruction types. Each instruction has two parts: Operation code (known as opcode) and operand. 2 OUT(10H), A Opcode to output data Operand to specify that the byte should be sent from the accumulator to port 10H

3. Machine Cycles and Bus Timings Assume that the instruction is stored in 2 Bytes The Z80 has to perform three operations: Read Byte 1 from the first memory location Read Byte 2 from the next memory location Send Data to port 10H 3 OUT(10H), A Opcode to output data Operand to specify that the byte should be sent from the accumulator to port 10H

4. Machine Cycles and Bus Timings Instruction the time required to complete the execution of an instruction. The Z80 instruction cycle consists of one to six machine cycles or one to six operations. Machine Cycle The time required to complete one operation of accessing memory, accessing I/O, or acknowledging an external request. This cycle may consist of three to six T-states. T-state One subdivision of operation performed in one clock period. These subdivisions are internal states synchronized with the system clock and each T-state is equal to one clock period. 4

5. Opcode Fetch Machine Cycle (M1) AddressMachine CodeInstructionComment 2002 01000111 2  (47H) LD B, ACopy A into B 5

6. Opcode Fetch Machine Cycle (M1) 6

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8. The Timing of the opcode Fetch Machine 8

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10. 10 The Timing of the opcode Fetch Machine

11. 11 The Timing of the opcode Fetch Machine

12. Memory Read Machine Cycle The instruction consists of two bytes; Opcode and Data byte. The Z80 must first read these bytes from memory Requires at least two machine cycles. The machine cycle is opcode fetch, and the second machine cycle is Memory Read 12

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16. Memory Write Cycle This is a one-byte instruction with two machine cycles: Opcode Fetch and Memory Write. Z80 fetches the code (77H) and it copies the byte 9FH from the accumulator into the memory location 2350H. 16

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20. Memory Interfacing 20

21. Interfacing Memory An address should be placed on the address lines. The low-order address lines are decoded by the internal decoder of the memory chip, and the addressed register is identified. The high-order address should be decoded to generate a Chip Select signal, and the memory chip is selected by asserting the Chip Select low. 21

22. Interfacing Memory To read from the addressed register, the should be asserted low to enable the output buffer, and then the data byte from the register will be placed on the I/O lines. To write into the addressed register, the should be asserted low to enable the input buffer, and then data bits from the data lines are stored into the register. 22

23. How does the Z80 Read from or Write into Memory? 23

24. Basic Concepts in Memory Interfacing Interface Function: Be able to select the chip Identify the register Enable the appropriate buffer. 24

25. Read from the Memory 25

26. Write into memory register 26

27. Address Decoding 3 input lines A0-A2 (Memory Select Buffer (MSB)) A3 – A7 are control lines since the address starts at F0H to F7H 3 lines enable only one o/p line 27 A7A6A5A4A3A2A1A0 11110111 = F7H

28. Example 1: Interfacing the 2764 EPROM Used in industry to develop microprocessor-based products. 8k (8192  8) memory chip with 8 data lines Housed in a 28-pin package. 28

29. Chip Configuration 29

30. What is the Memory Addresses Range? 30 A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0 0000000000000000 0001111111111111 0000 H  1FFF H

31. Interfacing CMOS 6116 Static R/W Memory This is a 2k static memory chip organized as 2048 x 8 format. It has 11 address lines (A10-A0), 8 data lines 3 control signals: 31

32. Chip Configuration 32

33. Memory Interface What is the addresses range? Assume A12 and A11 are do not care. 33 A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0 100XX00000000000 100XX11111111111 8000  87FF -- Address ranges may differ due to the do not care at A12 and A11

34. Reading Assignment Please Read Chapter 3 Chapter 4 34