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Example of Scheduling and Allocation based on Jaap Hofstede IIR Filter

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#define m1 … #define m2 … #define m3 … #define m4 … main() {float t, i1, o1, d1=0.0, d2=0.0; while (1) { in(i1); t = i1 + m3*d2 + m1*d1; o1 = t + m4*d2 + m2*d1; d2 = d1; d1 = t; out(o1); } Specification in C IIR Filter with 4 coefficients Recursive circuit

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Draw data flowgraph Original dataflow graph Memory elements

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#define m1 … #define m2 … #define m3 … #define m4 … main() {float t, i1, o1, d1=0.0, d2=0.0; while (1) { in(i1); t = i1 + m3*d2 + m1*d1; o1 = t + m4*d2 + m2*d1; d2 = d1; d1 = t; out(o1); } t This is example of wide class of circuits called linear systems with applications in communication, image processing, radar, control, robotics, prediction etc. See 573 class Please note the feedback loop in this circuit

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m1 + + + + i1 o1 D2 D1D2 D1 C8 C2 C7C1 C5C6C3C4 m3m2m4 ASAP (4 stages) := Calculate multipliers and adders with studentsASAP Feedback not shown output input

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m1 + + + + o1 D2 D1 C8 C2C7 C1C5C6 C3 C4 m3 m2m4 ALAP (4stages) D2 D1 := i1 Calculate multipliers and adders with studentsALAP

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m1 + + + + o1 D2 D1 C8 C2 C7 C1 C5 C6 C3 C4 m3 m2 m4 1 Adder, 1 multiplier (6 stages - tradeoff) D2 D1 := ??in adder i1 Calculate multipliers and adders with students Move operators

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m1 + + + + i1 o1 D2 D1 C8 C2 C7 C1 C5 C6 C3 C4 m3 m2 m4 1 Adder, 1 multiplier (6 stages) C1, C2 moved down D2 D1 := Move operators

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m1 + + + + o1 D2 D1 C8 C2 C7 C1 C5 C6 C3 C4 m3 m2 m4 N2N1 N2 loop pipeline 1 Adder, 1 multiplier (4 stages) loop pipeline D2 D1 := i1 Move operators, create pipeline, look at c 3 c 4 1 2 3 4

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m1 + + + + o1 D2 D1 C8 C2 C7 C1 C5 C6 C3 C4 m3 m2 m4 N2N1 N2 Registers 9 Registers included V1 V2 V6 V5 V3 V7 V8V9 D2 D1 := N1 V4 i1 Add pipeline registers v5 and v6 are compatible 1 2 There are many methods to add registers. Here we take into account feedbacks that are not shown. We assume the same delay for add and mul. Separate logic blocks with one register

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4321 V1 V3 V2 V4 V5 V6 V7 V8 V9 Analyze Lifetimes of registers 9 Registers included v5 and v6 are compatible Time steps V1 created in time 1 V1 used in time 2 and not used after V3 created in time 2

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55 1+1+ 88 7+7+ 22 66 9+9+ 4+4+ 3 := Lifetime compatibility graph (+ := is source of data) compatible v5 and v6 are compatible Find registers that are compatible, their cliques We can prove from this graph that creating a clique 5,7,8 would not lead to smaller number of registers Ri

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51 8726 9 4 3 R1 R2 R3 R5 R6 R4 Clique partitioning

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R2R6R5R4R1 R3 + O1 I1 1 2 3 4 R5R4R3R2R1 R2 R3 R5 R3 R1 R2R5 R4 m1 m3 m2 m4 R5 R4 1,3422 2,4 Corresponding non-optimised data path Numbers are time steps

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m1 + + + + o1 D2 D1 C8 C2 C7 C1 C5 C6 C3 C4 m3 m2 m4 N2N1 N2 V1 V2 V6 V5 V3 V7 V8V9 D2 D1 := N1 V4 i1 1 2

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R2R6R5R4R1 R3 + O1 I1 1 2 3 4 R5R4R3R2R1 R2 R3 R5 R3 R1 R2R5 R4 m1 m3 m2 m4 R5 R4 1, 3 422 2, 4 Corresponding non-optimised data path m1 + + + + o1 D2 D1 C8 C2 C7 C1 C5 C6C6 C3C3 C4 m3 m2 m4 N2 N1 N2 V1 V2 V6 V5 V3 V7 V8V9 D2 D1 := N1 V4 i1 Step 1 2 Step 2 Step 3 Step 4

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R2R6R5R4R1 R3 + O1 I1 1 2 3 4 R5R4R3R2R1 R2 R1 R5 R3 R1 R3 R2 R5 R4 m1 m3 m2 m4 R5 R4 1,3422 2,4 Multiplexers optimised by commutative property

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R2R6R5R4R1 R3 + O1 I1 1,3 2,4 1 2,3 4 1 2 3 4 1,4 2,3 R5R4R3R2R1 R5 R3 R1 R2 m1 m3 m2 m4 R5 R4 1,3422 2,4 I1 Size of multiplexers reduced M1 M2 M3 M4

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Design of Controller – stage 1 All six registers have an enable input, ena Rx.ena M1 and M4 have 1 control input, s: Mx.s M2 and M3 have 2 control inputs, s1 and s0: Mx.s1 and Mx.s0 Controller has four states: State1, State2, State3, State4

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Design of Controller – details All six registers have an enable input, ena Rx.ena M1 and M4 have 1 control input, s: Mx.s M2 and M3 have 2 control inputs, s1 and s0: Mx.s1 and Mx.s0 Controller has four states: State1, State2, State3, State4 R2R6R5R4R1 R3 + O1 I1 1,3 2,4 1 2,3 4 1 2 3 4 1,4 2,3 R5 R4R3R2R1 R5 R3 R1 R2 m1m1 m3m3 m2m2 m4m4 R5 R4 1, 3 422 2, 4 I1 M1 M2 M3 M4

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Design of Controller – stage 2 R1.ena = M1.s = M3.s0 = State2 + State4 R2.ena = R3.ena = State1 + State3 R4.ena = R5.ena = State2 R6.ena = M2.s1 = State4 M2.s0 = M4.s = State2 + State3 M3.s1 = State3 + State4

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Design of Controller – details R2R6R5R4R1 R3 + O1 I1 1,3 2,4 1 2,3 4 1 2 3 4 1,4 2,3 R5R4R3R2R1 R5 R3 R1 R2 m1m1 m3m3 m2m2 m4m4 R5 R4 1, 3 422 2, 4 I1 M1 M2 M3 M4 R1.ena = M1.s = M3.s0 = State2 + State4 R2.ena = R3.ena = State1 + State3 R4.ena = R5.ena = State2 R6.ena = M2.s1 = State4 M2.s0 = M4.s = State2 + State3 M3.s1 = State3 + State4 Controls of muxes

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Design of Controller – stage 2 R1.ena = M1.s = M3.s0 = State2 + State4 R2.ena = R3.ena = State1 + State3 R4.ena = R5.ena = State2 R6.ena = M2.s1 = State4 M2.s0 = M4.s = State2 + State3 M3.s1 = State3 + State4

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