Presentation is loading. Please wait.

Presentation is loading. Please wait.

Final Project : Pipelined Microprocessor Joseph Kim.

Similar presentations

Presentation on theme: "Final Project : Pipelined Microprocessor Joseph Kim."— Presentation transcript:

1 Final Project : Pipelined Microprocessor Joseph Kim

2 Project Goals Understand microprocessor design techniques –Branch Target Buffer (BTB) –Pipelining Create the fastest microprocessor possible within the design constraints

3 What is Pipelining? Divides the work for each instruction into stages Each stage is executing a different instruction Performance increases because the processor executes many instructions simultaneously

4 Problems with Pipelining Branch instructions Data Hazards –The needed data has not yet been calculated (interlocking) –The needed data is calculated, but not written (register bypass)

5 Solutions to the Branch Problem Delayed Branching Branch Squashing Branch Target Buffer

6 Project Description Five stage pipelined microprocessor Does not implement virtual memory functionality Does not use branch delaying Instead implements a branch target buffer

7 Five Stage Pipeline Stages: –Fetch –Decode –Execute –Memory Read/Write and BTB Update –Register file write Why Five?

8 Critical Path Longest delay in processor Our critical path is 16 ns Clock frequency is 59 MHZ

9 How the BTB works Global Register Cache of 2-bit counter values Cache of addresses

10 Data path

11 Performance Calculations

12 Overall Performance Instructions per second = Clock Frequency * CPI Our processor executes 59 MIPS

13 Concluding Remarks Modern microprocessor design techniques drastically increase performance A five stage pipeline with a branch target buffer gives our processor excellent performance at a reasonable cost

Download ppt "Final Project : Pipelined Microprocessor Joseph Kim."

Similar presentations

Ads by Google