Presentation on theme: "Final Project : Pipelined Microprocessor Joseph Kim."— Presentation transcript:
Final Project : Pipelined Microprocessor Joseph Kim
Project Goals Understand microprocessor design techniques –Branch Target Buffer (BTB) –Pipelining Create the fastest microprocessor possible within the design constraints
What is Pipelining? Divides the work for each instruction into stages Each stage is executing a different instruction Performance increases because the processor executes many instructions simultaneously
Problems with Pipelining Branch instructions Data Hazards –The needed data has not yet been calculated (interlocking) –The needed data is calculated, but not written (register bypass)
Solutions to the Branch Problem Delayed Branching Branch Squashing Branch Target Buffer
Project Description Five stage pipelined microprocessor Does not implement virtual memory functionality Does not use branch delaying Instead implements a branch target buffer
Five Stage Pipeline Stages: –Fetch –Decode –Execute –Memory Read/Write and BTB Update –Register file write Why Five?
Critical Path Longest delay in processor Our critical path is 16 ns Clock frequency is 59 MHZ
How the BTB works Global Register Cache of 2-bit counter values Cache of addresses
Overall Performance Instructions per second = Clock Frequency * CPI Our processor executes 59 MIPS
Concluding Remarks Modern microprocessor design techniques drastically increase performance A five stage pipeline with a branch target buffer gives our processor excellent performance at a reasonable cost
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