1. CSCE 212 Quiz 9 – 3/30/11 1.What is the clock cycle time based on for single-cycle and for pipelining? 2.What two actions can be done to resolve data hazards? 3.What the are 5 stages of the pipeline and what happens in each? Extra credit: For these instructions – add, beq, lw, sw – tell which stage(s), if any, of the pipeline that they do not use.

2. CSCE 212 Quiz 9 Answers 1.What is the clock cycle time based on for single-cycle and for pipelining? – Single-cycle: time of the longest instruction – Pipelining: time of the longest stage

3. CSCE 212 Quiz 9 Answers 2.What two actions can be done to resolve data hazards? – Forwarding – Stalling

4. CSCE 212 Quiz 9 Answers 3.What are the five stages of the pipeline and what happens in each? – IF: Fetch instruction – ID: Decode instruction and read register file – EX: Execute operation or calculate address – MEM: Access memory – WB: Write value to memory file

5. CSCE 212 Quiz 9 Answers Extra credit: For these instructions – add, beq, lw, sw – tell which stage(s), if any, of the pipeline that they do not use. – add: doesn’t use MEM – beq: doesn’t use WB – lw: uses all stages – sw: doesn’t use WB