2 Datapath and ControlControl Unit - Determines the enabling and sequencing of the operationsDatapath - performs data transfer and processing operationsThe control unit receives:– External control inputs– Status signalsThe control unit sends:– Control signals– Control outputs
3 Types of Control Unit 2 types: Programmable System Non-programmableProgrammable SystemInput consist of sequence of instructionsInstruction are usually stored in memory (RAM or ROM)Address comes from PC (Program Counter)Non-programmable (This chapter FOCUS on this)Control unit is NOT responsible for getting instructions from memory or sequencing, hence NO PCControl unit determines the operation based on inputs and status bit from the datapath.
4 ALGORITHMIC STATE MACHINE (ASM) The function of a state machine (or sequential circuit) can be represented by a state table or a state diagram.A flowchart is a way of showing actions and control flow in an algorithm.An Algorithmic State Machine (ASM) is simply a flowchart-like way to specify state diagrams for sequential logic and, optionally, actions performed in a datapath.While flowcharts typically do not specify “time”, an ASM explicitly specifies a sequence of actions and their timing relationships.
5 ALGORITHMIC STATE MACHINE (ASM) A Flowchart is a convenient way to specify a sequence of procedural steps and decision paths for an algorithm.ASM chart provides not only sequence of events, but it distinguished by the fact that it describes the timing relationship between states of the CU and the datapath actions in response to clock pulses.
7 ASM Chart : 1. State Box Consist of a rectangle with: The symbolic name for the state marked outside the upper left topContaining register transfer operations and outputs activated within or while leaving the stateAn optional state code, if assigned, outside the upper right topEntryExit
8 ASM Chart : 1. State Box Explanation: The register transfer indicates that the register R is to be reset to 0 on any clock pulse that occurs while the control is in state IDLE.RUN indicates that the ouput signal RUN is to be 1 during the time that the control in state IDLE.EntryExit
9 ASM Chart : 2. Scalar Decision Box (Refers to 1 bit condition)Consist of a diamond with:One input path (entry point).One input condition, placed in the center of the box, that is tested. (in this case START)A TRUE exit path taken if the condition is true (logic 1).A FALSE exit path taken if the condition is false (logic 0).EntryExit 0Exit 1
10 ASM Chart : 3. Conditional Output Box Consist of an oval with:One input path from a decision box or decision boxes.One output pathRegister transfers or outputs that occur only if the conditional path to the box is taken.
11 ASM Chart : 4. Vector decision box Consist of a hexagon with:One Input Path (entry point).A vector of input conditions, placed in the center of the box, that is tested.EntryExit 0Exit 1Exit 2Exit 2n - 1Up to 2n output paths. The path taken has a binary vector value that matches the vector input condition
12 ASM ChartTransfers and outputs in a state box are Moore type - dependent only on stateTransfers and outputs in a conditional output box are Mealy type - dependent on both state and inputs
13 ASM BlockConsist of ONE State box and all of the decision and conditional output box connected between the state box exit and entry paths to the same or other boxes.Figure 8.2 : Morris Mano,pg 367
14 ASM Block State IDLE, AVAIL = 1 START = 0, next state is IDLE ANALYSIS:State IDLE, AVAIL = 1START = 0, next state is IDLESTART = 1, next state, A is cleared to all 0’sDepending on value of Q(1:0), next state is MUL0, MUL1, MUL2 or MUL3.Note : The entry path and the five exit paths for the ASM block is labeled at the boundaries of the ASM block
15 ASM Block : Another Example ANALYSIS:State IDLE, AVAIL = 1START = 0, next state is to Increase R and next state is IDLESTART = 1, next to clear R to all 0’s and next state is…Depending on value of Q0, next state is MUL0 or MUL1.1
16 ASM Timing Considerations Fig. 8.3 : Morris Mano,pg 368Refer to Figure 8.2Using PGT, the timing diagram below is obtained.
17 ASM Timing Considerations Fig 8.3 AnalysisClock cycle 1Present state = IDLEOutput AVAIL = 1Input START = 0NEXT clock cycle (beginning of clock cycle 2 PGT)Content of Reg A unchanged, AVAIL = 1ASM Timing Considerations
18 ASM Timing Considerations Fig 8.3 AnalysisClk cycle 2 (PGT)Present state = IDLESTART = 1NEXT clock cycle (beginning of clock cycle 3 PGT)Reg A = is cleared to 0Q(1:0) is examined = 01So path MUL1 is takenASM Timing Considerations
19 ASM Timing Considerations Fig 8.3 AnalysisClk cycle 3 (PGT)Present state = MUL1Reg A = 0ASM Timing Considerations
20 ASM Timing - Conclusion Outputs appear while in the state(in response to state and input values)Register transfers occur at the clock while exiting the state – So, new value occur in the next state!