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1 PIPELINE AND VECTOR PROCESSING CHAPTER # 9. 2 CONTENTS Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector.

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Presentation on theme: "1 PIPELINE AND VECTOR PROCESSING CHAPTER # 9. 2 CONTENTS Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector."— Presentation transcript:

1 1 PIPELINE AND VECTOR PROCESSING CHAPTER # 9

2 2 CONTENTS Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector Processing Array Processors

3 3 Figure 9-1 Processor with multiple functional units Integer multiply Adder-sub tractor Floating-point multiply Floating-point divide Floating-point Add-subtract Incrementer Logic unit Shift unit Processor register To memory

4 4 Instruction and stream. Single instruction stream, single data stream (SISD). Single instruction stream, multiple data stream (SIMD). Multiple instruction stream, single data stream (MISD). Multiple instruction stream, multiple data stream (MIMD).

5 5 Figure 9-2 Example of Pipelining. A i B i C i R 1 A i, R 2 B i Input A i and B i R 3 R 1 * R 2, R 4 C i Multiply and input C i R 5 R 3 + R 4 Add C i to product R1R1 R2R2 Multiplier R3R3 R4R4 Adder R5R5

6 6 Clock Pulse number Segment1 R1 R2 Segment2 R3 R4 Segment3 R5 1 A 1 B A 2 B 2 A 1 *B 1 C A 3 B 3 A 2 *B 2 C 2 A 1 *B 1 +C 1 4 A 4 B 4 A 3 *B 3 C 3 A 2 *B 2 +C 2 5 A 5 B 5 A 4 *B 4 C 4 A 3 *B 3 +C 3 6 A 6 B 6 A 5 *B 5 C 5 A 4 *B 4 +C 4 7 A 7 B 7 A 6 *B 6 C 6 A 5 *B 5 +C A 7 *B 7 C 7 A 6 *B 6 +C A 7 *B 7 +C 7 Table 9-1 Content of registers in pipeline example.

7 7 Figure 9-3 Four segment pipeline. Clock Input R4R4 S1S1 R3R3 R2R2 S4S4 S3S3 S2S2 R1R1

8 8 Figure 9-4 Space-time diagram for pipeline T1T2T3T4T5T6 T1T2T3T4T5T6 T1T2T3T4T5T6 T1T2T3T4T5T6 Clock cycle Segment:

9 9 Figure 9-5 Multiple functional units in parallel. P4 I i+3 P3 I i+2 P2 I i+1 P1 IiIi

10 10 Arithmetic Pipeline Compare the exponents. Align the mantissas. Add or subtract the mantissas. Normalize the result.

11 11 Mantissas Exponents a b A B Segment 1 Segment 2 Segment 3 Segment 4 R Compare Exponent By subtraction R R Choose exponent R Adjust Exponent R R Align mantissas R R Add or subtract mantissas Normalize result R Difference Figure 9-6 Pipeline for floating-point and subtraction.

12 12 Instruction Pipeline Fetch the instruction from memory. Decode the instruction. Calculate the effective address. Fetch the operands from memory. Execute the instruction. Store the result in the proper place.

13 13 Figure 9-7 Four-segment CPU pipeline. Segment 1 Segment 2 Segment 3 Segment 4 Decode instruction And calculate Effective address Fetch instruction from memory Branch? Fetch operand From memory Execute instruction Interrupt? Interrupt handling Update PC Empty pipe yes no yes no

14 14 FI is the segment that fetches an instruction. DA is the segment that decodes the instruction and calculate the effective address. FO is the segment that fetches the operand. EX is the segment that executes the instruction. Segments and their purpose.

15 Step: Instruction: (Branch) FI DA FO EX FI DA FO FI DA EX FO DA FI FI Figure 9-8 Timing of instruction pipeline.

16 16 Pipeline Conflicts Resource conflicts Data dependency conflicts Branch difficulties conflicts

17 17 Three-segment instruction pipeline I: Instruction fetch A: ALU operation E: Execute instruction

18 18 Delayed Load LOAD R1 M[address 1] LOAD R2 M[address 2] ADD R3 R1+R2 STORE M[address 3] R3

19 19 E Figure 9-9 Three segment pipeline timing.

20 20 Figure 9-10 Examples of delayed branch. Using no-operation instructions

21 21 I Clock cycles I I A A A E E E 1. Load 2. Increment 4. Add 5. Subtract 3. Branch to X 6. Instruction in X I A I A E E I A E Figure 9-10 Examples of delayed branch. Rearranging instruction

22 22 Application of Vector Processing Long range weather forecasting. Petroleum explorations. Seismic data analysis. Medical diagnosis. Aerodynamics and space flight simulations.

23 23 Figure 9-11 Instruction format for vector processor Operation code Base address Source 1 Base address Source 2 Base address destination Vector length

24 24 Figure 9-12 Pipeline for calculating an inner product Source A Source B Multiplier pipeline Adder pipeline

25 25 Figure 9-13 Multiple module memory organization AR DR Memory array Memory array Memory array Memory array Address bus Data bus

26 26 Types of Array Processors Attached Array Processor SIMD Array Processor

27 27 Figure 9-14 Attached Array Processor with host computer General-Purpose computer input-output interface Attached array processor Local memoryMain memory High-speed memory to Memory bus

28 28 Figure 9-15 SIMD array processor organization Master control unit Main memory PE 1 PE 2 PE 3 PE n M1M1 M2M2 M3M3 MnMn


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