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Logic System Design I More on Decoders and Muxes ECGR2181 Lecture Notes 2A 01001110010000110101001101010101.

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Presentation on theme: "Logic System Design I More on Decoders and Muxes ECGR2181 Lecture Notes 2A 01001110010000110101001101010101."— Presentation transcript:

1 Logic System Design I More on Decoders and Muxes ECGR2181 Lecture Notes 2A

2 Making Larger Components Consider destination then use component given to work toward solution. Think about the functionality of the destination component Think about what the given parts can do Then, bring it all together Finally, once design is done make a couple of test cases to see if the design is valid. If not, repeat from start. 2A-2Logic System Design I

3 Making Large Muxes i.e., construct a 16-input mux from any number of 4-input muxes 2A-3Logic System Design I 16-input Multiplexer i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 i8i8 i 10 i9i9 i 11 i 12 i 14 i 13 i 15 S0S0 S2S2 S1S1 S3S3 Y 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y ???

4 Example Continued T.T. Goal: 2A-4Logic System Design I 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 i8i8 i 10 i9i9 i 11 i 12 i 14 i 13 i 15 S3S3 S2S2 S1S1 S0S0 Y Z?Z? 0000i0i0 0001i1i1 0010i2i2 0011i3i3 0100i4i4 0101i5i5 0110i6i6 0111i7i7 1000i8i8 1001i9i9 1010i i i i i i 15 Z3Z3 Z2Z2 Z1Z1 Z0Z0 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 Z0Z0 Z1Z1 Z2Z2 Z3Z3 Z0Z0 Z1Z1 Z2Z2 Z3Z3 Z0Z0 Z1Z1 Z2Z2 Z3Z3 Z0Z0 Z1Z1 Z2Z2 Z3Z3 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y Y S2S2 S3S3 Z3Z3 Z2Z2 Z1Z1 Z0Z0

5 Signal Flow Illustrated 2A-5Logic System Design I S3S3 S2S2 S1S1 S0S0 Y 0000i0i0 0001i1i1 0010i2i2 0011i3i3 0100i4i4 0101i5i5 0110i6i6 0111i7i7 1000i8i8 1001i9i9 1010i i i i i i 15 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 i8i8 i 10 i9i9 i 11 i 12 i 14 i 13 i 15 Z3Z3 Z2Z2 Z1Z1 Z0Z0 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 Y S2S2 S3S3 Z3Z3 Z2Z2 Z1Z1 Z0Z0 If S=7, then Y will equal the value on i 7 = i 3 = i 11 = i 15 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y

6 2A-6Logic System Design I Signal Flow Illustrated, again S3S3 S2S2 S1S1 S0S0 Y 0000i0i0 0001i1i1 0010i2i2 0011i3i3 0100i4i4 0101i5i5 0110i6i6 0111i7i7 1000i8i8 1001i9i9 1010i i i i i i 15 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 i8i8 i 10 i9i9 i 11 i 12 i 14 i 13 i 15 Z3Z3 Z2Z2 Z1Z1 Z0Z0 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 Y S2S2 S3S3 Z3Z3 Z1Z1 Z0Z0 Z2Z2 If S=9, then Y will equal the value on i 9 = i 1 = i 5 = i 13 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y

7 2A-7Logic System Design I Enable Lines T.T. Goal: i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 i8i8 i 10 i9i9 i 11 i 12 i 14 i 13 i 15 G S3S3 S2S2 S1S1 S0S0 Y 0xxxx i0i i1i i2i i3i i4i i5i i6i i7i i8i i9i i i i i i i 15 Z3Z3 Z2Z2 Z1Z1 Z0Z0 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 Y S2S2 S3S3 Z3Z3 Z2Z2 Z1Z1 Z0Z0 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G G S1S1 S0S0 Y 0xx0 1 00i0i0 1 01i1i1 1 10i2i2 1 11i3i3 G G G G G

8 2A-8Logic System Design I Enable Lines, Continued 16-input Mux, w/ 2 enable inputs {1 active-high (G 0 ) & 1 active-low (G 1 )} i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 i8i8 i 10 i9i9 i 11 i 12 i 14 i 13 i 15 G1G1 G0G0 S3S3 S2S2 S1S1 S0S0 Y x0xxxx0 1xxxxx i0i i1i i2i i3i i4i i5i i6i i7i i8i i9i i i i i i i 15 Z3Z3 Z2Z2 Z1Z1 Z0Z0 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 Y S2S2 S3S3 Z3Z3 Z2Z2 Z1Z1 Z0Z0 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G = 0 Disabled State Enabled State For devices with multiple Enable inputs, all Enables must be asserted for the device operate as per it’s definition.

9 2A-9Logic System Design I Enable Lines, Continued i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 i8i8 i 10 i9i9 i 11 i 12 i 14 i 13 i 15 G1G1 G0G0 S3S3 S2S2 S1S1 S0S0 Y x0xxxx0 1xxxxx i0i i1i i2i i3i i4i i5i i6i i7i i8i i9i i i i i i i 15 Z3Z3 Z2Z2 Z1Z1 Z0Z0 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 S0S0 S1S1 Y S2S2 S3S3 Z3Z3 Z2Z2 Z1Z1 Z0Z0 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G G0G0 G0G0 G0G0 G0G0 G1G1 16-input Mux, w/ 2 enable inputs {1 active-high (G 0 ) & 1 active-low (G 1 )}

10 The New Mux Here is a the TT & symbol for our shinny new 16-input Mux, with 2 enable lines 2A-10Logic System Design I G1G1 G0G0 S3S3 S2S2 S1S1 S0S0 Y x0xxxx0 1xxxxx i0i i1i i2i i3i i4i i5i i6i i7i i8i i9i i i i i i i input Multiplexer i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 i8i8 i 10 i9i9 i 11 i 12 i 14 i 13 i 15 S0S0 S2S2 S1S1 S3S3 Y G0G0 G1G1

11 Mux Implementation of Combinational Logic Make an inverter out of a 4-input Mux 2A-11Logic System Design I G S1S1 S0S0 Y 0xx0 1 00i0i0 1 01i1i1 1 10i2i2 1 11i3i3 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G Vcc G1’G1’G1G1 G1G1 G1’G1’ Start with the Mux, keep an eye on the TT. Configure the inputs such that … when G1 = ‘0’ the output will equal ‘1’ and, when G1 = ‘1’ the output will equal ‘0’ Enable the Mux always. Never leave unused inputs unconnected.

12 More complex design … F(a,b,c) For a 8-input mux the output can be described as Y = i 0 (S 2 ’S 1 ’S 0 ’) + i 1 (S 2 ’S 1 ’S 0 ) + i 2 (S 2 ’S 1 S 0 ’) + i 3 (S 2 ’S 1 S 0 ) + … … + i 4 (S 2 S 1 ’S 0 ’) + i 5 (S 2 S 1 ’S 0 ) + i 6 (S 2 S 1 S 0 ’) + i 7 (S 2 S 1 S 0 ) 1. Connect the inputs of the function (a,b,c) to the select lines of the mux … with a connected to S 3 Y = i 0 (a’b’c’) + i 1 (a’b’c) + i 2 (a’bc’) + i 3 (a’bc) + i 4 (ab’c’) + i 5 (ab’c) + i 6 (abc’) + i 7 (abc) 2A-12Logic System Design I Mux Implementation of Boolean Expression Continued 

13 2A-13Logic System Design I 8-input Multiplexer i0i0 i2i2 i1i1 i3i3 i4i4 i6i6 i5i5 i7i7 S0S0 S2S2 S1S1 Y G0G0 G1G1 2.Connect the inputs to the mux (i 7 – i 0 ) to one or zero depending upon the value in the truth table For F(a,b,c) =  m(0,2,5,7)... i 0 =1; i 1 =0; i 2 =1; i 3 =0; i 4 =0; i 5 =1; i 6 =0; i 7 =1 F(a,b,c) = 1(a’b’c’) + 0(a’b’c) + 1(a’bc’) + 0(a’bc) + 0(ab’c’) + 1(ab’c) + 0(abc’) + 1(abc) F(a,b,c) = a’b’c’ + a’bc’ + ab’c + abc F(a,b,c) = m 0 + m 2 + m 5 + m 7 Mux Implementation of Boolean Expression (cont.) Begin by connecting the system inputs (a,b,c) to the select lines as described above Vcc Connect the minterms where the function equals ‘1’ to Vcc Connect the remaining mux inputs to gnd Connect the enable lines to the appropriate Vcc or gnd to always enable the mux c a b F Connect the output of the mux to the output of the system (F)

14 More Mux Implementation of Comb. Logic Implement F(x,y,z) = Σm(3,4,6,7) using a 4-input mux 2A-14Logic System Design I 4-input Mux i0i0 i2i2 i1i1 i3i3 S0S0 S1S1 Y G xyzF x y Connect the most significant two inputs to the select lines Pairs of minterms (where x & y remain constant) are then considered For xy = 00, the output F is independent of z … i 0 should be connected to gnd. For xy = 01, the output F is dependent on z … when z = 0, F = 0 and when z = 1 F = 1; thus i 1 = z z z For xy = 10, the output F is dependent on z … when z = 0, F = 1 and when z = 1 F = 0; thus i 2 = z’ For xy = 11, the output F is independent of z … F = 1 for both cases of z … i 3 should be connected to Vcc Vcc Enable mux and connect the output of the mux to F F

15 More on Decoders Recap: When enabled: the input combination value (i) is the subscript of the output that is asserted. Otherwise, the output is zero. Where i is i 1 & i 0 concatenated. When not enabled all outputs are zero. Making larger decoders: A decoder is used to select the appropriate output decoder 2A-15Logic System Design I 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 Gi1i1 i0i0 y3y3 y2y2 y1y1 y0y0 0xx

16 Expanding Decoders 3x8 Decoder using only 2x4 decoders 2A-16Logic System Design I Gi2i2 i1i1 i0i0 y7y7 y6y6 y5y5 y4y4 y3y3 y2y2 y1y1 y0y0 0xxx x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 3 x8 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 i2i2 y4y4 y6y6 y5y5 y7y7 ??? 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1

17 3x8 Decoder 2A-17Logic System Design I 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y1y1 y2y2 y3y3 y4y4 y5y5 y6y6 y7y7 Gi2i2 i1i1 i0i0 y7y7 y6y6 y5y5 y4y4 y3y3 y2y2 y1y1 y0y0 0xxx Connect the outputs as shown Connect the least significant inputs to the inputs of the output decoders i1i1 i0i0 i1i1 i0i0 Each combination of i 1 & i 0 will produce two asserted outputs; thus, we need to enable the decoder with the desired output and disable the others … 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 Connect the first level decoder shown based on the remaining inputs. In this case, i 2 of the new decoder. When i 2 = 0, the top decoder is enabled. When i2 = 1 the bottom decoder is enabled. z0z0 z0z0 z1z1 z1z1 i2i2 Connect the enable for the new decoder to the enable of the first level mux. G NOTE: Unused inputs must connect to something … unused outputs are left hanging.

18 4x12 Decoder (non-std.) Decode binary word to 1-of-12 code (12 outputs) 2A-18Logic System Design I GG 0 _Li3i3 i2i2 i1i1 i0i0 y 11 y 10 y9y9 y8y8 y7y7 y6y6 Y5Y5 y4y4 y3y3 y2y2 y1y1 y0y0 x1Xxxx xXxxx

19 4-to-12 Decoder (non-std.) 2A-19Logic System Design I 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y1y1 y2y2 y3y3 y4y4 y5y5 y6y6 y7y7 i1i1 i0i0 i1i1 i0i0 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 z0z0 z0z0 z1z1 z1z1 i2i2 i3i3 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y8y8 y9y9 y 10 y 11 i1i1 i0i0 z2z2 z2z2 G 0 _L 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 G1G1 Vcc G int

20 4-to-16 Decoder 4x16 Decoder with an active-high enable 2A-20Logic System Design I 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y1y1 y2y2 y3y3 y4y4 y5y5 y6y6 y7y7 i1i1 i0i0 i1i1 i0i0 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 z0z0 z1z1 i2i2 i3i3 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y8y8 y9y9 y 10 y 11 i1i1 i0i0 z2z2 z0z0 z1z1 z2z2 z3z3 G 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 Y 12 y 13 y 14 y 15 i1i1 i0i0 z3z3 4x 16 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y4y4 y6y6 y5y5 y7y7 y8y8 y 10 y9y9 y 11 y 12 y 14 y 13 y 15 i2i2 i3i3

21 Demultiplexer (demux) A demux performs the reverse operation from the mux The demux routes one input to 1-of-n outputs based on the select-line input combination System description for 4 output demux (2 select-lines) y 0 = i·s 1 ’·s 0 ’ y 1 = i·s 1 ’·s 0 y 2 = i·s 1 ·s 0 ’ y 3 = i·s 1 ·s 0 Recall from the decoder a description could be given as follows: y 0 = G·s 1 ’·s 0 ’ y 1 = G·s 1 ’·s 0 y 2 = G·s 1 ·s 0 ’ y 3 = G·s 1 ·s 0 2A-21Logic System Design I

22 Demux (concluded) 2A-22Logic System Design I You can see, from the previous expressions, that the demux could be implemented with a decoder that has an enable Just connect I to G of the decoder and you have a demux. Warning: Most CAD tools rely on the user knowing this fact … … the libraries do not contain any demuxes, just decoders. 2x4 decoder y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y1y1 s0s0 s1s1 y2y2 i y3y3 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y1y1 0 0 y2y2 i y3y3 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y1y1 1 0 y2y2 i y3y3 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y1y1 0 1 y2y2 i y3y3 y0y0 y2y2 y1y1 y3y3 G i0i0 i1i1 y0y0 y1y1 1 1 y2y2 i y3y3


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