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Decoders

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Usage of Decoders Channel Selection: Generates Mutually Exclusive Channel Enabling/Disabling Signals (e.g. Multiplexers) Device Selection: Generates unique 1’s/0’s on output lines to turn on/off devices (e.g. decoder trees) Universal Function Implementation: Serves as a device for implementing Boolean Functions on a Universal Basis Coding and Decoding Information: Can be used in a code/decode process (inputs can be recognized solely from outputs

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Functional Description and Symbols

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Where, N = {1, 2, 3, …..}

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Truth Table for a n-to-m Line Decoder

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Truth Table for a n-to-m Line Decoder (with enable)

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Where, m = 2 (n+1) – 1 n = {0,1, 2, 3, ….., ∞} Block-Symbol for n-to-m Line Decoders

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Truth Table for a 1-to-2 Line Decoder

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Block-Symbol for 1-to-2 Line Decoders

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Truth Table for a 2-to-4 Line Decoder

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Block-Symbol for 2-to-4 Line Decoders

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Truth Table for a n-to-m Active-Low Line Decoder

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Truth Table for a n-to-m Line Active-Low Decoder (with enable)

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Where, m = 2 (n+1) – 1 n = {0,1, 2, 3, ….., ∞} Block-Symbol for n-to-m Line Active-Low Decoders

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Decoder Trees

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A Larger Decoder using smaller Decoders 2-to-4 Line Decoder using 1-to-2 Line Decoders

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Device On/Off Truth Table

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A Decoder Tree operates on the principle of unique device selection by a Decoder i.e. the Decoders in the final level/stage are used for generating the unique outputs as required, while decoders in the previous stages are employed for device selection (in this case the devices are decoders in the final stage).

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Logical Truth Table of Decoder Tree

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3-to-8 Line Decoder using 1-to-2 & 2-to-4 Line Decoders

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Boolean Function Realization

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Function Implementation Using Decoders

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To implement the function we ‘OR’ the output pins d 0 and d 2 (which correspond to the Minterms m0 and m2). Using Relationships established using Duality f’ = m1 + m3 f = [ m1 + m3 ] ’ f = m0 + m2 F(x1, x2, …., xn) = ∑m R = ∏M S [F(x1, x2, …., xn)]’ = ∑m S = ∏M R

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Function Implementation Using Decoders f’ = m1 + m3 f = [ m1 + m3 ] ’ f = m0 + m2

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Function Implementation Using Active-Low Decoders

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To implement the function we ‘OR’ the output pins d 0 and d 2 (which correspond to the Minterms m0 and m2). Using Relationships established using Duality f’ = M0. M2 f = [ M0. M2 ] ’ f = M1. M3 F(x1, x2, …., xn) = ∑m R = ∏M S [F(x1, x2, …., xn)]’ = ∑m S = ∏M R

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Function Implementation Using Active-Low Decoders f’ = M0. M2 f = [ M0. M2 ] ’ f = M1. M3

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Multiple Output Function Implementation Using Decoders

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COE 202: Digital Logic Design Combinational Circuits Part 3 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Ahmad Almulhem, KFUPM.

COE 202: Digital Logic Design Combinational Circuits Part 3 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Ahmad Almulhem, KFUPM.

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