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– 1 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 SPICE Simulation of Generalized Return Ratio (GRR) vs. Loop Gain (LG)

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Trans-Impedance Amplifier (TIA) – 2 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 I C1 = 1 mA R C = 10 kΩ R F = 20 kΩ β = 200 V A = 1000 V R μ = 1 MΩ C π = 0.3 pF C μ = 100 fF C CS = 100 pF

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GRR Simulation w/ Output Break Point – 3 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 RR V RR I

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RR V & RR I w/ Output Break Point – 4 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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GRR Simulation w/ Input Break Point – 5 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 RR V RR I

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RR V & RR I w/ Input Break Point – 6 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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GRR (RR -1 = RR V -1 + RR I -1 ) – 7 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Loop-Gain Simulation – 8 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Product of two voltage gains is the loop gain (why?) V t driving at InputV t driving at Output

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GRR vs. LG – 9 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Nyquist Diagram – 10 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 *Generalized Return-Ratio Calculation *Comparison of RR to Loop-Gain Simulation *A simple model of BJT w/o capacitance.MODEL npn NPN +IS=1.0E-16 BF=200 VAF=1000 RB=0 *The basic TIA sub-circuit used in sim..subckt TIA V1 V2 V3 V4 Q1 V2 V1 GND NPN M=1 Rmu V1 V2 1x Cpi V1 GND 0.3p Cmu V1 V2 100f Ccs V2 GND 100p RC VCC V2 10k RF V3 V4 20k *Bias up the circuit w/ ideal I and bypass C ICC GND VCC 1.005m CCC GND VCC 1.ends TIA *Calculate the gen. RR *Break loop open at output, voltage drive XOV OV1 OV2 OV1 OV4 TIA LOV OV2 OV4 1e3 COV OV4 OV3 1 VOV OV3 GND AC=1 *Break loop open at output, current drive XOI OI1 OI2 OI1 OI4 TIA COI OI2 GND 1 LOI OI2 OI4 1e3 IOI GND OI4 AC=1 *Break loop open at input, voltage drive XIV IV1 IV2 IV3 IV2 TIA LIV IV1 IV3 1e3 CIV IV1 IV4 1 VIV IV4 GND AC=1 *Break loop open at input, current drive XII II1 II2 II3 II2 TIA LII II1 II3 1e3 CII II3 GND 1 III GND II1 AC=1 *Calculate the loop-gain w/ direct voltage drive XLI LI1 LI2 LI1 LI2 TIA CLI LI3 LI1 1 VLI LI3 GND AC=1 XLO LO1 LO2 LO1 LO2 TIA CLO LO3 LO2 1 VLO LO3 GND AC=1.op.ac dec 10 1e3 1e12 *Derive RR from the gen. output terminal.probe ac RRO=par('(v(OV2)*i(COI))/(v(OV2)+i(COI))') *Derive RR from the gen. input terminal.probe ac RRI=par('(v(IV3)*i(CII))/(v(IV3)+i(CII))') *Derive loop-gain by multiplying two gains.probe ac LG=par('v(LI2)*v(LO1)').option nomod nopage captab post acout=0 ingold=2.temp 25.end

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