ISA (4) ARC Registers ARC has 32 general purpose registers from r0 to r32 –However, r0 is set to value 0 and cannot be changed. –We can use all the other registers. Using registers is very easy ! Just refer to their contents using the “%” symbol. E.g., Consider the instruction: andcc %r1 %r2 %r3 In English this stands for: “Compute the logical bitwise AND of the contents of register r1 and register r2 and store in register r3” If we don’t use the %, the assembler will return a syntax error.
ISA (4) User-Visible Registers Stack Pointer: we will study later. PC: program counter, next instruction to execute
ISA (4) ARC Memory Using memory is not so straightforward as registers, but is still quite easy. –If you enclose a memory location in “[ ]” it refers to the contents of the memory –Else it refers to the actual memory location. Consider a Java (or C/C++ statement) int x = 10; In ARC, we can allocate this memory as x: 10 Now, to access the content of this memory we must enclose “x” in “[ ]” –E.g., Consider the instruction: ld [x] %r1 // “Load the contents of memory location x in register r1” On the other hand, if we do not enclose x within the “[ ]”, then –With “ld” and “st” instructions you will get a syntax error. These instructions require memory content, not data ! –With “call” instruction it will end up calling the actual location of the memory. E.g., call x ; // here it will call the instruction located at memory location “x”
ISA (4) Summary so far … We looked at: –ARC instructions –Using registers –Using memory. Lets look at a few ARC programs on the simulator and then get our hands dirty into how the assembly code is actually represented.
ISA (4) Example program Memory locations are represented within [ ] ld and st are the only two operations allowed on memory. These are information for the assembler. They are not part of the assembly language
ISA (4) Instruction Format Every ARC instruction is 32 bits in length. –For instance, the instruction below must fit within 32 bits when represented in binary. –To do this, ARC enforces certain formats that allow us to use the 32 bits in different ways. These are called instruction formats. –A format defines how the various bit fields of an instruction are laid out within 32 bits and how it is interpreted by the ARC control unit.
ISA (4) ARC Pseudo-Ops Pseudo-ops are instructions to the assembler. They are not part of the ISA.
ISA (4) Adding 5 integers ….org 3000 a: 10 25 2 3 4 a_start: 3000 counter: 0 output: 0 ld [a_start], %r1 ! Load the starting address of a into %r1 ld [counter], %r2 ! Register r2 is the counter. andcc %r3,%r0, %r3 ! What does this do? loop: subcc %r2, 5, %r0 ! Have we reached the end of the array? be done ! If %r2 – 5 = 0, exit loop. addcc %r2, 1, %r2 ! Increment counter ld %r1, %r4 ! Load the number from the array addcc %r4, %r3, %r3 ! Accumulate sum into %r3. addcc %r1, 4, %r1 ! Goto next address ba loop done: st %r3, [output] jmpl %r15+4, %r0
ISA (4) Summary Storage location for address of the array a. Having this location allows us to load the address “3000” into a register. Length is being used as a “counter” to determine when to end the loop.
ISA (4) Other ARC instructions Software traps: –Allows programs to invoke services from the OS/hardware, e.g., reading a keyboard or writing onto a display. –ARC has trap instructions – but they do not control the OS/hardware (due to JVM limitations).
ISA (4) Summary Assembly programming 101 Different language, but still within same paradigm