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CPSC 330 Fall 1999 HW #1 Assigned September 1, 1999 Due September 8, 1999 Submit in class Use a word processor (although you may hand-draw answers to Problems.

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Presentation on theme: "CPSC 330 Fall 1999 HW #1 Assigned September 1, 1999 Due September 8, 1999 Submit in class Use a word processor (although you may hand-draw answers to Problems."— Presentation transcript:

1 CPSC 330 Fall 1999 HW #1 Assigned September 1, 1999 Due September 8, 1999 Submit in class Use a word processor (although you may hand-draw answers to Problems 24 and 25) Chapter 2, Heuring and Jordan, Prob: 2, 3, 4, 5, 6, 9, 14, 23, 24, 25

2 2.3 T is a memory location used as a temporary 3-address 2-address 1-address 0-address ADD A,B,C LOAD A,B LDA D PUSH D ADD T,D,E ADD A,C ADD E PUSH E MPY A,A,T LOAD T,D STA T ADD ADD T,E LDA B PUSH C MPY A,T ADD C PUSH B MPY T ADD STA A MPY POP A

3 2.4 Assume that operands and results are stored in memory addresses can be accessed with direct addressing. Also assume that SRC has a multiply instruction, mpy, that uses format 6. ld r0, B ld r1, C add r0, r0, r1 ld r1, D ld r2, E add r1, r1, r2 mpy r0, r0, r1 st r0, A

4 2.5 Assume each instruction fetch requires one memory access Machine Instructions Opnds/Results Total 3-address address 5 13* 18 1-address address SRC (gen reg) *ADD A, C takes 3 data accesses: 2 to fetch A and C and one to store A

5 address: Each instruction has one 8-bit opcode field and three 24-bit memory address fields, so one instruction needs 10 bytes. Three instructions = 30 bytes. 2-address: Each instruction has one 8-bit opcode field and two 24-bit memory address fields. One instruction needs 7 bytes, so five require 35 bytes. 1-address: Each instruction has one 8-bit opcode field and one 24-bit memory address field. One instruction needs 4 bytes, so eight require 32 bytes. 0-address: One arithmetic instruction only requires one 8-bit opcode field. One PUSH/POP instruction requires one 8-bit and one 24-bit memory address field, so three arithmetic instructions require 3 bytes and five PUSH/POP instructions require 20 bytes. Total 23 bytes. SRC: One load/store instruction requires 8-bit opcode field, one 5-bit register number field, and one 24-bit memory address field, so one load/store instruction requires 5 bytes. One arithmetic instruction requires one 8-bit opcode field and three 5-bit register number fields, so one arithmetic instruction requires 3 bytes. Therefore. five load/store instructions and three arithmetic instructions require 5 * * 3 = 34 bytes.

6 2.9 In a stack machine, an arithmetic instruction only needs an opcode field, while a PUSH/POP instruction needs both opcode and a much longer address field. If all instructions were forced to be the same length, a considerable amount of memory space would be wasted in arithmetic instructions.

7 2.14 a) ld r0, a ; Get value of a la r1, 1 ; Gt constant +1 lar r2, plus ; Set branch target brzr r2, r0 ; Skip next if a=0 neg r1, r1 ; Convert constant to -1 plus: add r0, r0, r1 ; Form a+1 or a-1 st r0, a ; Update a b) la r4, 0 ; Constant 0 la r3, ndigit ; R[3] points to ndigit[i] lar r2, loop ; Branch target addi r1, r4, 0 ; Make R[1], =i, 0 loop: st r4, 0(r3) ; ndigit[i] = 0 addi r3, r3, 4 ; Advance array pointer addi r1, r1, 1 ; i++ addi r0, r1,-10 ; R[0]<0 iff i<10 brmi r2, r0 ; Repeat if i<10

8 2.23 Register Transfer Control signals a) W <- R[6]+1 R[6]out, Win Y <- W Wout, Yin Z <- R[4] + Y R[4]out, Zin R[3] <- Z Zout, R[3]in b) Y <- R[5] R[5]out, Yin Z <- R[4] + Y R[4], Zin Y <- Z Zout, Yin Z <- R[3] + Y R[3]out, Zin R[2] <- Z Zout, R[2]in

9 2.24 On whiteboard 2.25 On whiteboard


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