1. The Emerging Electronic Design Automation Design Technology Needs for Supporting Emerging Reaches of Silicon Rajesh Gupta, UC San Diego gupta@ucsd.edu http://www.cse.ucsd.edu/~gupta

2. 2 12/18/03 R. Gupta, UC San Diego A Chip Is A Wonderful Thing! A typical chip, circa: 2006 l50 square millimeters l50 million transistors l1-10 GHz, 100-1000 MOP/sq mm, 10-100 MIPS/mW l300 mm, 10,000 units/wafer, 20K wafers/month l$5 per part Does not matter what you build lProcessor, MEMS, Networking, Wireless, Memory lSo there is a strong incentive to port your application, system, box to the “chip”

3. 3 12/18/03 R. Gupta, UC San Diego The Technology and Its Industry Components Systems Tools Masks Mask data Source: IBS 2003

4. 4 12/18/03 R. Gupta, UC San Diego The EDA Industry lCurrent EDA market n$1B Synthesis and verification –$400M synthesis, $400M verification, $200M Emulation n$2.7in PDA, IP and Design Services. l8% Y-Y growth in Q2/2003 nMore like 6.0% for tool licenses (85% of revenue) lRevenue Drivers for EDA nSemiconductor R&D spending nDesign completion activity nSemiconductor capital expenditures (backend EDA tools)  Good chips and more chips lead to EDA growth

5. 5 12/18/03 R. Gupta, UC San Diego But it costs $20M to build one… ÜNot a problem, until you consider this… Source: IBS 2003

6. 6 12/18/03 R. Gupta, UC San Diego “Disaggregation” in Semis lOf the 72 distinct application markets that rely on value added IC designs (ASIC, ASSP, FPGA, SOC) nover 50% are less than $500M n75% are less than $1B lManufacturing is no longer a competitive advantage Source: IBS

7. 7 12/18/03 R. Gupta, UC San Diego Rising Fabless, Fablite lCurrently at $20B nabout 15% of the semiconductor market ngoing up to 50% by 2006 lDesign technology needs are not the same as those of high value part manufacturers nExample: Baseband and CMOS Radio Source: Teresa Meng, Atheros

8. 8 12/18/03 R. Gupta, UC San Diego A Changing Industry lStructural Changes nOutsourcing: Fabrication, Design Implementation lTechnological Changes nNew materials and devices being explored to overcome the roadmap “brickwalls” nThe mega-investments into nanotechnology –History tells us that fundamental device discoveries happen within a relatively short period of time –All major components of IC today were invented within a 10-year period from the Shockley transistor in 1947 –But a long development cycle for manufacturing (more on it later)

9. 9 12/18/03 R. Gupta, UC San Diego …Dragging EDA Along With It l(Rapidly) Falling ASIC Starts nFrom 10K in 1996 to about 2K in 2005 lRise of FPGAs and Deep Deep Submicron Noise nCan lead to shrinking or at best stationary market in ICs l“EDA moving from expansion to retention phase.” n[Desai, Industry Update, Nov 2003] lMore and more it is EDA consuming itself nRevenue reallocation within the same block: Verification, Synthesis nMajor portions of EDA revenues are business with itself nBasic value proposition is being lost lOTOH, Dataquest predicts 15% growth based on ESL expansion nThe record there is not so good so far –Compilers, embedded systems, software –Embedded software is about a $1B lAre we becoming irrelevant?

10. 10 12/18/03 R. Gupta, UC San Diego What Must EDA Do? A Three-Point Prescription: ŒUnderstand the new silicon Enable box makers expand reach of silicon ŽUnderstand that marketplace is not everything

11. 11 12/18/03 R. Gupta, UC San Diego The New Semi Characteristics lHighly application specific ndomain specific IC design, focus on system level lContent increasingly determines processing n“embedded intelligence” through embedded software lConnection more important than processing nbandwidth delivery more important than computational efficiency 1

12. 12 12/18/03 R. Gupta, UC San Diego New Semi Challenges lNeed streamlined/simplified system architectures ngain from scalability, adaptability, not from design complexity nThe technology favors concurrency than speed lDesign reuse, design closure and sign-off nmake IP viable through software value add and platform ownership lKey technical challenges nProductivity, Power, Heterogeneous Integration, Test  Getting it right means many more systems capabilities through Software 1

13. 13 12/18/03 R. Gupta, UC San Diego Design Decisions Are Important 1 Source: Teresa Meng

14. 14 12/18/03 R. Gupta, UC San Diego And Likelihood of Failure High 1

15. 15 12/18/03 R. Gupta, UC San Diego Engineering Moving Up lChip Engineering Moving Up and Moving Down nSystems Engineering versus Silicon Engineering lSilicon Engineering Hot-buttons nDesign for Manufacturing nDefect-tolerant Design lEDA has been so far supporting Silicon Engineering nWith lip-service to System Engineering 1

16. 16 12/18/03 R. Gupta, UC San Diego Systems Engineering Example Problem: How to achieve high throughput in a SOC for wireless applications? lCan select a modem sub-system nthat packs more bits/Hz, but it will tolerate less noise and be less robust so that link throughput may not improve lCan increase transmit power in RF subsystem nto improve robustness but this increases energy cost, reduces network capacity, and requires more expensive analog circuits (power amps) lCan reduce bits/frame nto tolerate higher bit error rates (BER) and provide more robustness, but this may increase overhead and queuing delays lCan increase precision in digital modem nto reduce noise, but this leads to wider on-chip busses and more power consumption  Getting it right (within engineering constraints) is the task of “Systems Engineering” 1

17. 17 12/18/03 R. Gupta, UC San Diego Expanding Semiconductor Use 2

18. 18 12/18/03 R. Gupta, UC San Diego Future Silicon Proliferation lFrom Computers, Communications to nGaming, Robotics, Biomedical, … Instrumented wide-area spaces Personal area spaces Internet end-points In-body, in-cell, in-vitro spaces lGoing Forward Si Has Place in Major Human Endeavors nCommunications: Wireless, Sensor networks, open spectrum nEntertainment: Virtual worlds, education, multimedia delivery nMedicine and Biology: lab-on-chip, devices & disability assists nTransportation: automotive, avionics nPhysical Sciences: big science, life sciences nExploration: space, oceanic 2

19. 19 12/18/03 R. Gupta, UC San Diego Accelerating Proliferation 2 Near Future: < 5 years Going Forward: > 5 years

20. 20 12/18/03 R. Gupta, UC San Diego Environmental Monitoring lSanta Margarita Ecological Reserve, SMER n4,334 acre field station 50 miles NE of San Diego with variety of habitat, terrain lA testbed for 56 ongoing experiments including sensing –Hydrology (stream flow, temp, pH, O2, conductivity..) –Microclimate, fire hazard –Chemical, biological agents lHigh Performance Wireless Research and Education Network n45 Mbps wireless backbone running across southern CA connecting –SMER, Mt. Palomar, IGPP/SIO seismic network nReal-time environmental monitoring –Seismic, oceanographic, hydrological, ecological data nhttp://hpwren.ucsd.edu 2

21. 21 12/18/03 R. Gupta, UC San Diego Santa Margarita Ecological Reserve Source, Dan Cayan, UCSD SIO 2 Water Chemistry Quality Stations

22. 22 12/18/03 R. Gupta, UC San Diego Drive Integration: BioChem Labs. lCrisis detection, evolutionary monitoring, genotyping lComputation+Networking+Sensing nIn-package integration of microfluidic, communications, networking and processing subsystems nRemotely operated, reconfigurable laboratories for biochemical analysis lSub-systems nBiofluidic sample preparation, transport, disposal nChemical analysis, biological assays nIn-situ monitoring, control, communication, adaptation 2

23. 23 12/18/03 R. Gupta, UC San Diego Going Forward…On-Chip Chemistry 2 lIC-like microfluidic processors for handling complex biofluids & self-calibration (BioFlips) nMicropumps, flow sensors, viscosity sensors, diffusion assayes, laminar flow-based target extractors, flow cytometers.

24. 24 12/18/03 R. Gupta, UC San Diego Drive IC Into Fabrics and Buildings Ember radios and networks 2 Source: Ember Networks

25. 25 12/18/03 R. Gupta, UC San Diego Systems Engineering through EDA Consider “Wireless SOC” lPlatforms: OMAP, PCA, MXC nBasic theme: lMerging hardware: Heterogenous MP on-chip –Separating software Communications, networking, applications nIn the process, a lot of legacy stuff is left in as “overheads” –Multiple UI functions, fragmented memory system and shared memory processor locks 2 1

26. 26 12/18/03 R. Gupta, UC San Diego Multiple Heterogenous On-Chip lSoftware development is a challenge with evolving processors lShared memory processing lUse OS and API support to provide a “usable” programming model lDivergent approaches nTI: Integrate DSP, single programming environment nIntel, Motorola: Separate Comm, Networking, App. lWhat is the right programming model for these systems? 2 1

27. 27 12/18/03 R. Gupta, UC San Diego ESL Technology Needs lThese are needs that will turn technology capacity afforded by new chips into new systems capabilities ŒComponents and Compositional Correctness nA posteriori validation is simply not possible Software and Software Infrastructure nHardware capabilities and constraints driving need for new software architecture nNew “awareness” into software infrastructure –Energy, Location, Reactivity, Precision, Security 2 1

28. 28 12/18/03 R. Gupta, UC San Diego 1 Compositional Correctness lBuild “Complete” System Models nThat includes the application and system software nAdapt, control and debug applications nExplore the full potential of SOC architectural platforms –e.g., by exploring applications, networking and communication subsystems together lHow? Through “Component Composition Framework” (CCF) nDefine compositional semantics –enable easy system construction and its “formal” validation –“adequate”, hierarchical and verifiable composition –Create “Virtual” System Architectures nLeverage advances in programming languages and verification. 2 1

29. 29 12/18/03 R. Gupta, UC San Diego 2 Software and Its Infrastructure lChanges in structure of system software nOS moving towards micro-kernels –Services moved to processes (e.g., Nucleus, Symbian) –Still legacy remains: memory, file semantics as unifying theme for communications. lChanges in division of labor among nApplication, middleware, operating system nCompiler, runtime lChallenges in bringing new capabilities and contract into the system software 2 1

30. 30 12/18/03 R. Gupta, UC San Diego Consider Energy “Awareness” lWhat does it mean to be aware? nServices “know” about energy, power –File system, memory management, process scheduling –Make each of them energy aware lHow does one make software to be “aware”? nUse “reflectivity” in software to build adaptive software nAbility to reason about and act upon itself (OS, MW) lMake middleware adaptive to respond to application requirements nand to dynamically smooth the imbalances between demand and availability of energy resource 2 1

31. 31 12/18/03 R. Gupta, UC San Diego What Must EDA Do? A Three-Point Prescription: ŒUnderstand the new silicon Enable box makers expand reach of silicon ŽUnderstand that marketplace is not everything

32. 32 12/18/03 R. Gupta, UC San Diego EDA Technology and Marketplace lBy and large EDA technology moves through startups and acquisitions nOne of the few industries where the business plans do not always call for sustainable standalone business lThe driver for EDA industry growth is Semiconductor R&D lMajor semi innovations happened in the industry labs. 3 TransistorBell Labs1947 Single crystalWestern Elect.1950 Zone refiningWestern Elect.1950 Grown junction, Silicon junctionWE, TI1951, 1955 Oxide masking, diffusionWE1955 Planar transistor process, ICFairchild, TI1960, 1961 Ion implantation, plasma processing, E-beam AT&T Bell Labs.

33. 33 12/18/03 R. Gupta, UC San Diego Semi. R&D Is Changing Rapidly lShrinking, vanishing industry research laboratories lIndustry resorting to consortia to carry out needed technology innovations and developments nOften with substantial government support nSEMATECH, SELETE, ASET, MEDIA, ITRI, HsinChuPark,… 3

34. 34 12/18/03 R. Gupta, UC San Diego Sematech Experience & EDATech lUS Semiconductor industry gradually lost share starting late 70’s lBy 1985, it lost leadership. Semi equipment vendors were loosing share about 5% per year lIts fate was pretty much sealed until the industry and Reagan administration decided to do something about “The Rising Sun” lThe industry worked hard to define a “precompetitive space” lSupported the supplier industry to semi houses n$100M per year, for 8 years until 1994 n$800M investment by the government, $100M per year lBy 1994, the industry assumed its leadership position.

35. 35 12/18/03 R. Gupta, UC San Diego Summary lThe new Silicon comes out of the fab fast and furious nOur ability to implement and manufacture vastly exceeds our capability to architect, reason and validate the new generation of silicon systems lOur challenge is to make sure what goes into manufacturing has tremendous value-add to end application (systems) nSoftware is the defining IP nBut it is a whole new ballgame: new awareness, fangled, adaptive, … lR&D leadership necessary to turn Si advantage into new systems capabilities nNew applications as reflected in new forms of computing –Cognitive, Mobile, Entertainment, Embedded, Wireless, Trusted/secure computing, and so on. lIf left alone, the gap between our systems capabilities and new Si possibilities will continue to widen.

36. 36 12/18/03 R. Gupta, UC San Diego Questions to ponder lWhat is the right precompetitive space for EDA? nFrameworks nBackend backplane nData format standards nLanguage, libraries, models, models of computation lWhat is the next big application space for Semis? nLab-on-chip, smart fabrics, appliances, robotics lWhat are the training needs for the EDA professional? And where will the jobs be? nSystems engineering, Nanotechnology, Biology, Chemistry lWhat is “Plan B” for EDA? nHow can EDA expand beyond supplier to Semis?