1. 1CADENCE DESIGN SYSTEMS, INC. SCE-MI 2.0, Cadence Summary (Accellera ITC Meeting) Feb 17, 2005

2. 2 SCE-MI CPD Meets ITC Stated Goals* Support for Variable-Length Messages (VLMs) –Eases task of writing BFMs –Enables SCE-MI infrastructure to optimize transport of VLMs Eliminate Uncontrolled Clock –Eases task of writing BFMs Backward Compatibility –Maintain SCE-MI 1.0 functionality, 1.0 & 2.0 BFMs can coexist –Maintain focus on performance * SCE-MI CPD has been investigated and proven by Cadence in the context of customers’ verification systems

3. 3 Native VLM Support Simplifies BFM assign messageWordOut = mQ[currMessageWord]; assign transmitLast = (transmitReady && (currMessageWord == lastMessageWord)); always @(posedge uclock) begin if (readyForCclock == 0) begin if (outReceiveReady) begin readyForCclock <= 1; outTransmitReady <= 0; end else if (cclockEnabled) begin if (newMessageGenerated) begin currMessageWord <= 0; transmitReady <= 1; end if (outReceiveReady == 0) readyForCclock <= 0; else begin if (transmitLast) transmitReady <= 0; if (transmitReady) begin currMessageWord <= currMessageWord + 1; end SCE-MI 1.0 assign messageWordOut = mQ[currMessageWord]; assign transmitLast = (transmitReady && (currMessageWord == lastMessageWord)); always @(posedge cclock) begin if (newMessage) begin currMessageWord <= 0; transmitReady <= 1; newMessage <= 0; end Always @(posedge cclock) begin if (transmitLast) transmitReady <= 0; if (transmitReady) currMessageWord <= currMessageWord + 1; end SCE-MI CPD VLM macro eliminates clock control Interaction of multiple message ports compounds problem in 1.0

4. 4 Native VLMs Enable Higher Performance SCE-MI Infrastructure can optimize VLM transport Multiple message words transferred across HW/SW interface in one operation Hardware-Side (Emulator) handles message segmentation for input ports, aggregation for output ports SCE-MI 1.0 SCE-MI CPD SW Side HW Side SW Side HW Side

5. 5 SCE-MI 2.0: Desirable Characteristics Language Neutrality –C/C++ –Synthesizable Verilog/VHDL/SystemVerilog Platform Neutrality –Simulation/Acceleration, Event-Based/Cycle-Based Support Ease-of-Use/Performance trade-off –SCE-MI 1.0/2.0 compatibility and co-existence allows selection of appropriate mechanism * These characteristics are embodied in the Cadence-Proposed Draft (CPD) and Cadence’s implementation of same

6. 6 Language Neutrality SCE-MI CPD maintains SCE-MI language neutrality RTL SW SideHW Side C/C++ TLM C/C++ TLM SCE-MI macro proxy Abstract proxies easily created for SW-side (e.g. TLM) Standard RTL on HW-side supported by a broad range of vendors and applications

7. 7 Platform Neutrality Use of CPD macros eliminate the need for clock control Unbounded “Zero-Time Operations” do not exist Sim Kernel wait() SW SideHW Side SW side and HW side run in a single-process simulation schedService() serviceLoop()

8. 8 1.0/CPD Compatibility CPD macro semantics can be defined in terms of 1.0 macros –Ease support for SCE-MI 1.0 vendors –Ensure compatibility of 1.0/CPD semantics SceMiMessageOutPort TransmitReady Message ReceiveReady SceMiClockControl ReadyForCclock SceMiClockPort Cclock ClockNum=N SceMiVarMessageOutPort Clock TransmitReady Message TransmitLast ww+1

9. 9 Streaming for Performance Steaming allows longer free-run times in emulator Slightly modified isReady semantics enable streaming Applicable to non-reactive tests SW Side HW Side 3 isReady Deferred isReady

10. 10 SCE-MI CPD Incremental Improvement AttributeSCE-MI 1.0SCE-MI CPD Additions SCE-MI – CPD In Aggregate Performance+ Fundamentally + ZTOs supported + VLMs can be optimized by infrastructure + Fundamentally + VLMs can be optimized by infrastructure + ZTOs supported Usability+ Callback mechanism usable (proven) + uclock/cclock provides flexibility for BFM writers + Implicit clock control simplifies BFMs + VLM simplifies BFMs + Callback mechanism usable (proven) + Implicit clock control simplifies BFMs + VLM simplifies BFMs + uclock/cclock provides flexibility for BFM writers Language Neutrality + C/C++, VHDL/Verilog/SystemVerilog + (no change)+ C/C++, VHDL/Verilog/SystemVerilog Platform Neutrality - uclock/cclock mechanism problematic in simulation + Implicit clock control enables platform neutrality +/- Depending on use model (limiting to CPD additions enables platform neutrality)

11. 11 SCE-MI CPD Exceeds ITC Stated Goals Support for Variable-Length Messages (VLMs) Eliminate Uncontrolled Clock Backward Compatibility Platform Neutrality Streaming Capable for Performance