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1 Why Johnny Can’t Code Preparing Engineers for Billion Gate Designs Mike Keating.

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Presentation on theme: "1 Why Johnny Can’t Code Preparing Engineers for Billion Gate Designs Mike Keating."— Presentation transcript:

1 1 Why Johnny Can’t Code Preparing Engineers for Billion Gate Designs Mike Keating

2 2 Interview Question assign D = A && B; (posedge clk) begin C <= D; end A B C clk D (posedge clk) begin C <= A && B; end 2x the processes = 2x the complexity

3 3 Why Code Size Matters Designers inject approx. 1 defect per 10 lines of code Excellent code ships with ~1 defect per KLOC 100M LOC

4 4 Typical RTL Code

5 5 Unstructured Verilog Code assign … … (posedge clk …) … assign … … assign … (posedge clk …) … …

6 6 Unstructured Verilog Code assign … … // get packet (posedge clk …) … assign … … assign … // send packet (posedge clk …) … … It’s like majoring in assembly language programming with emphasis on the “goto” statement

7 7 Model of Structured Code void bar () { f1 (); } void foo () { bar (); } main () { foo (); } class bar_class () { …; } class foo_class () { … } main () { constructors for classes … } Too much code? function f (); … endfunction task get_packet (); my_var2 <= g (…); endtask task send_packet (); my_var1 <= f (…); endtask (posedge clk …) begin get_packet (); send_packet (); end module bar_module (); …; endmodule module foo_module (); … endmodule top_module (); instantiate modules … endmodule Acts as “main”

8 8 Code Size Counts – DCT Example Verilog 95 Lines of code1541 Files9 Sequential processes 6 Assign statements 149 Combinational processes 6 Tasks0 Functions0

9 9 Code Size Counts – DCT Example Verilog 95SystemVerilog Lines of code Files91 Sequential processes 61 Assign statements 1490 Combinational processes 62 Tasks04 Functions08

10 10 Code Size Counts – DCT Example Verilog 95SystemVerilogSynthesizable C Lines of code Files911 Sequential processes 61 Assign statements 1490 Combinational processes 62 Tasks04 Functions08

11 11 Real-time reactive designs (USB, PCI Express) require a more sophisticated form of structured design

12 12 Structured Sequential Code - FSMs + { f (state, inputs) } State machine along with a set of combinational functions

13 13 High Level Synthesis #include int block[8][8]; void dct(){ int y,x,u,v; int reg[8]; /* Horizontal */ for(y=0;y<8;y++){ for(x=0;x<8;x++) reg[x]=0; for(x=0;x<8;x++){ for(u=0;u<8;u++){ v=block[y][x]*c[x][u]; v+=2048; v>>=12; if(s[x][u]) v=-v; reg[u]+=v; } State Machine Set of Arithmetic Functions

14 14 Hierarchical State Machines + { f (state, inputs) } Hierarchical State machine along with a set of combinational functions

15 15 Hardware Model of Structured Code function f (); … endfunction function g (); … endfunction (posedge clk …) case (state) IDLE: …; S0: begin if (f(input_x)) doit_x(); if (doit_x_done) state<= S2; end endcase task doit_x(); doit_x_done = 0; case (doit_x_state) S0: … Sn: begin … doit_x_done = 1; doit_x_state = S0; end endcase } Sub_state Machines

16 16 USB Example – DMA Processing Verilog 2k Lines of code1600 Files1 Sequential processes 7 Assign statements 30 Combinational processes 10 Tasks0 Functions0 State Space2 56 About 28 pages – too big! Massive Concurrency Impossibly large state space

17 17 USB Example – DMA Processing Verilog 2kSystemVerilog Lines of code Files11 Sequential processes 72 Assign statements 300 Combinational processes 100 Tasks02 Functions019 State Space /3 smaller Much Less Concurrency Dramatically smaller state space

18 18 Improving RTL Code

19 19 How to use structure to reduce code size and design complexity –SystemVerilog –Structs, enumerated types, interfaces –Functions, tasks How to measure state space and understand cost of verifying complex designs How to design and code hierarchical state machines to minimize state space What Students Need to Know

20 20 WHAT EDA NEEDS TO DO

21 21 More Interview Questions (*) begin C = A && B; E = C && D; end A B E C D (posedge clk …) begin W <= ……..; end (posedge clk …) begin X <= ……..; end (posedge clk …) begin Y <= ……..; end (posedge clk …) begin Z <= ……..; end Silly Does not model hardware Where’s the latch? Silly No good encapsulation mechanism (System)Verilog is not a good hardware design language – just better than VHDL or SystemC

22 22 Domain Specific Languages

23 23 (System)Verilog is NOT Domain Specific for Design bit_ff bit_comb state_machine Verilog: wires reg’s (which are not registers) SystemVerilog bit logic Both: whether a variable is a flop, latch or logic gate is determined by how it is used reg d; always_comb d = a | b;

24 24 Raising Abstraction of Design SystemVerilog C++/SystemC Gap is too big language, methodology, tools General Purpose, High Level Modeling Languages General Purpose Simulation Language Design-specific language for multiple levels of abstraction

25 25 It’s All Mission Critical

26 26 It’s all about Code Source: IBS Design Implementation 7/09


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