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ECE 555 Digital Circuits & Components ECE555 Lecture 8/9 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1.

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Presentation on theme: "ECE 555 Digital Circuits & Components ECE555 Lecture 8/9 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1."— Presentation transcript:

1 ECE 555 Digital Circuits & Components ECE555 Lecture 8/9 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1

2 ECE 555 Digital Circuits & Components Outline Adder Carry Ripple Manchester Carry Carry Bypass (or Skip) Carry Select Paralle Prefix Brent-Kung Kogge-Stone Delay and Power Comparisons 2

3 ECE 555 Digital Circuits & Components Single-Bit Addition 3 Half Adder Full Adder ABC out S ABC S

4 ECE 555 Digital Circuits & Components Single-Bit Addition 4 Half Adder Full Adder ABC out S ABC S

5 ECE 555 Digital Circuits & Components PGK For a full adder, define what happens to carries Generate: C out = 1 independent of C G = Propagate: C out = C P = Kill: C out = 0 independent of C K = 5

6 ECE 555 Digital Circuits & Components PGK For a full adder, define what happens to carries Generate: C out = 1 independent of C G = A B Propagate: C out = C P = A B Kill: C out = 0 independent of C K = ~A ~B Co(G,P) = G+PC i S(G,P) = P C i 6

7 ECE 555 Digital Circuits & Components Full Adder Design I Brute force implementation from eqns S=ABC i +ABC i +ABC i +ABC i = C i (AB+AB)+C i (AB+AB) C o =AB+BC i +AC i =(AB+BC i +Ac i ) 7

8 ECE 555 Digital Circuits & Components Full Adder Design II Factor S in terms of C o S = ABC i + (A + B + C i )(~C o ) Critical path is usually C i to C o in ripple adder 8 B BB BB B B B A A A A A A A A CiCi CiCi CiCi CiCi CiCi !C o !S CoCo S

9 ECE 555 Digital Circuits & Components Full Adder Design III 9 B!B Identical Delays for Carry and Sum P!P Signal set-up B A !B P A Carry generation Sum generation C in !P !C out !P P C in P A !C out P !P S C in

10 ECE 555 Digital Circuits & Components Carry-Ripple Adder Simplest design: cascade full adders Critical path goes from C i to C o Design full adder to have fast carry delay Worst case delay linear with the number of bits t d = O(N) t adder = (N-1)t carry + t sum 10

11 ECE 555 Digital Circuits & Components Inversion Property 11

12 ECE 555 Digital Circuits & Components Mirror Adder Critical path passes through majority gate Built from minority + inverter Eliminate inverter and use inverting full adder 12

13 ECE 555 Digital Circuits & Components Mirror Adder Cell 13 B BB BB B B B A A A A A A A A CiCi CiCi CiCi CiCi CiCi !C o !S

14 ECE 555 Digital Circuits & Components Fast Carry Chain Design 14 The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generatedG i = A i & B i = A i B i propagatedP i = A i B i (sometimes use A i | B i ) annihilated (killed)K i = !A i & !B i Giving a carry recurrence of C i+1 = G i | P i C i C 1 = C 2 = C 3 = C 4 =

15 ECE 555 Digital Circuits & Components Fast Carry Chain Design 15 The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generatedG i = A i & B i = A i B i propagatedP i = A i B i (sometimes use A i | B i ) annihilated (killed)K i = !A i & !B i Giving a carry recurrence of C i+1 = G i | P i C i C 1 = G 0 | P 0 C 0 C 2 = G 1 | P 1 G 0 | P 1 P 0 C 0 C 3 = G 2 | P 2 G 1 | P 2 P 1 G 0 | P 2 P 1 P 0 C 0 C 4 = G 3 | P 3 G 2 | P 3 P 2 G 1 | P 3 P 2 P 1 G 0 | P 3 P 2 P 1 P 0 C 0

16 ECE 555 Digital Circuits & Components Manchester Carry Chain 16 Switches controlled by G i and P i Total delay of time to form the switch control signals G i and P i setup time for the switches signal propagation delay through N switches in the worst case GiGi PiPi !C i !C i+1 clk

17 ECE 555 Digital Circuits & Components 4-bit Sliced MCC Adder 17 GP !C 0 clk GPGPGP & & & & A0A0 B0B0 A1A1 B1B1 A2A2 B2B2 A3A3 B3B3 S0S0 S1S1 S2S2 S3S3 !C 1 !C 2 !C 3 !C 4

18 ECE 555 Digital Circuits & Components Domino Manchester Carry Chain Circuit 18 C i,0 G0G0 clk P0P0 P1P1 P2P2 P3P3 G1G1 G2G2 G3G3 C i, !(G 0 | P 0 C i,0 ) !(G 1 | P 1 G 0 | P 1 P 0 C i,0 ) !(G 2 | P 2 G 1 | P 2 P 1 G 0 | P 2 P 1 P 0 C i,0 ) !(G 3 | P 3 G 2 | P 3 P 2 G 1 | P 3 P 2 P 1 G 0 | P 3 P 2 P 1 P 0 C i,0 )

19 ECE 555 Digital Circuits & Components Carry-Skip (Carry-Bypass) Adder 19 If (P 0 & P 1 & P 2 & P 3 = 1) then C o,3 = C i,0 otherwise the block itself kills or generates the carry internally A0A0 B0B0 S0S0 C i,0 FA A1A1 B1B1 S1S1 A2A2 B2B2 S2S2 A3A3 B3B3 S3S3 C o,3 BP = P 0 P 1 P 2 P 3 Block Propagate

20 ECE 555 Digital Circuits & Components Carry-Skip Chain Implementation 20 BP block carry-in block carry-out carry-out C in G0G0 P0P0 P1P1 P2P2 P3P3 G1G1 G2G2 G3G3 !C out BP

21 ECE 555 Digital Circuits & Components 4-bit Block Carry-Skip Adder 21 Worst-case delay carry from bit 0 to bit 15 = carry generated in bit 0, ripples through bits 1, 2, and 3, skips the middle two groups (B is the group size in bits), ripples in the last group from bit 12 to bit 15 C i,0 Sum Carry Propagation Setup Sum Carry Propagation Setup Sum Carry Propagation Setup Sum Carry Propagation Setup bits 0 to 3bits 4 to 7bits 8 to 11bits 12 to 15 T add = t setup + B t carry + ((N/B) -1) t skip +(B -1)t carry + t sum

22 ECE 555 Digital Circuits & Components Carry Select Adder 22 4-b Setup 0 carry propagation 1 carry propagation1 0 multiplexerC in C out Sum generation PsGs Cs Precompute the carry out of each block for both carry_in = 0 and carry_in = 1 (can be done for all blocks in parallel) and then select the correct one Ss

23 ECE 555 Digital Circuits & Components Carry Select Adder: Critical Path 23 Setup 0 carry 1 carry 1 0 mux C in Sum gen PsGs Cs Ss AsBs Setup 0 carry 1 carry mux Sum gen PsGs Cs Ss AsBs Setup 0 carry 1 carry mux Sum gen PsGs Cs Ss AsBs Setup 0 carry 1 carry mux C out Sum gen PsGs Cs Ss AsBs bits 0 to 3bits 4 to 7bits 8 to 1bits 12 to 15

24 ECE 555 Digital Circuits & Components Carry Select Adder: Critical Path 24 Setup 0 carry 1 carry 1 0 mux C in Sum gen PsGs Cs Ss AsBs Setup 0 carry 1 carry mux Sum gen PsGs Cs Ss AsBs Setup 0 carry 1 carry mux Sum gen PsGs Cs Ss AsBs Setup 0 carry 1 carry mux C out Sum gen PsGs Cs Ss AsBs bits 0 to 3bits 4 to 7bits 8 to 1bits 12 to T add = t setup + B t carry + N/B t mux + t sum

25 ECE 555 Digital Circuits & Components Square Root Carry Select Adder 25 Setup 0 carry 1 carry 1 0 mux C in Sum gen PsGs Cs Ss AsBsAsBs Ss Setup 0 carry 1 carry mux Sum gen PsGs Cs AsBs Setup 0 carry 1 carry mux C out Sum gen PsGs Cs Ss AsBs bits 0 to 1bits 2 to 4 bits 5 to 8bits 9 to 13 Setup mux Sum gen PsGs Cs Ss 1 carry 0 carry Setup 0 carry 1 carry mux Sum gen PsGs Cs AsBs bits 14 to 19 Ss

26 ECE 555 Digital Circuits & Components Square Root Carry Select Adder 26 Setup 0 carry 1 carry 1 0 mux C in Sum gen PsGs Cs Ss AsBsAsBs Ss Setup 0 carry 1 carry mux Sum gen PsGs Cs AsBs Setup 0 carry 1 carry mux C out Sum gen PsGs Cs Ss AsBs bits 0 to 1bits 2 to 4 bits 5 to 8bits 9 to 13 Setup mux Sum gen PsGs Cs Ss 1 carry 0 carry Setup 0 carry 1 carry mux Sum gen PsGs Cs AsBs bits 14 to 19 Ss T add = t setup + 2 t carry + N t mux + t sum

27 ECE 555 Digital Circuits & Components Adder Delays - Comparison 27

28 ECE 555 Digital Circuits & Components Parallel Prefix Adders (PPAs) 28 Define carry operator on (G,P) signal pairs is associative, i.e., [(g,p) (g,p)] (g,p) = (g,p) [(g,p) (g,p)] (G,P) where G = G PG P = PP

29 ECE 555 Digital Circuits & Components Parallel Prefix Adders (PPAs) 29 (G i:j,P i:j ) = (G i:k +P i:k G k-1:j, P i:k P k-1:j )

30 ECE 555 Digital Circuits & Components Parallel Prefix Adders (PPAs) 30 C o,0 = G 0 +P 0 C i,0 C o,1 = G 1 +P 1 C o,0 = G 1 +P 1 (G 0 +P 0 C i,0 ) = G 1 +P 1 G 0 +P 1 P 0 C i,0 = [G 1 + P 1 G 0 ]+[P 1 P 0 ]C i,0 = G 1:0 +P 1:0 C i,0 C o,2 = G 2 +P 2 C o,1 C o,3 = G 3 +P 3 C o,2 = G 3 +P 3 (G 2 +P 2 C o,1 ) = G 3 +P 3 G 2 +P 3 P 2 C o,1 ) = [G 3 +P 3 G 2 ]+ [P 3 P 2 ]C o,1 = G 3:2 +P 3:2 C o,1 = G 3:2 +P 3:2 (G 1:0 +P 1:0 C i,0 ) = [G 3:2 +P 3:2 G 1:0 ]+[P 3:2 P 1:0 ]C i,0 ) = G 3:0 +P 3:0 C i,0

31 ECE 555 Digital Circuits & Components PPA General Structure Measures to consider number of cells tree cell depth (time) tree cell area cell fan-in and fan-out max wiring length wiring congestion delay path variation (glitching) 31 P i, G i logic (1 unit delay) S i logic (1 unit delay) C i parallel prefix logic tree (1 unit delay per level) Given P and G terms for each bit position, computing all the carries is equal to finding all the prefixes in parallel (G 0,P 0 ) (G 1,P 1 ) (G 2,P 2 ) … (G N-2,P N-2 ) (G N-1,P N-1 ) Since is associative, we can group them in any order but note that it is not commutative

32 ECE 555 Digital Circuits & Components Brent-Kung PPA 32 Parallel Prefix Computation G0P0G0P0 G1P1G1P1 G2p2G2p2 G3P3G3P3 G4P4G4P4 G5P5G5P5 G6P6G6P6 G7P7G7P7 G8P8G8P8 G9p9G9p9 G 10 P 10 G 11 p 11 G 12 P 12 G 13 p 13 G 14 p 14 G 15 p 15 C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 C7C7 C8C8 C9C9 C 10 C 11 C 12 C 13 C 14 C 15 C 16 C in T = log 2 N T = log 2 N - 2 A = 2log 2 N A = N/2

33 ECE 555 Digital Circuits & Components Brent-Kung PPA 33 Parallel Prefix Computation G0P0G0P0 G1P1G1P1 G2p2G2p2 G3P3G3P3 G4P4G4P4 G5P5G5P5 G6P6G6P6 G7P7G7P7 G8P8G8P8 G9p9G9p9 G 10 P 10 G 11 p 11 G 12 P 12 G 13 p 13 G 14 p 14 G 15 p 15 C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 C7C7 C8C8 C9C9 C 10 C 11 C 12 C 13 C 14 C 15 C 16 C in T = log 2 N T = log 2 N - 2 A = 2log 2 N A = N/2

34 ECE 555 Digital Circuits & Components Kogge-Stone PPF Adder 34 Parallel Prefix Computation G0P0G0P0 G1P1G1P1 G2P2G2P2 G3P3G3P3 G4P4G4P4 G5P5G5P5 G6P6G6P6 G7P7G7P7 G8P8G8P8 G9P9G9P9 G 10 P 10 G 11 P 11 G 12 P 12 G 13 P 13 G 14 P 14 G 15 P 15 C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 C7C7 C8C8 C9C9 C 10 C 11 C 12 C 13 C 14 C 15 C 16 C in T = log 2 N A = log 2 N A = N T add = t setup + log 2 N t + t sum

35 ECE 555 Digital Circuits & Components More Adder Comparisons 35

36 ECE 555 Digital Circuits & Components Adder Speed Comparisons 36

37 ECE 555 Digital Circuits & Components Adder Average Power Comparisons 37

38 ECE 555 Digital Circuits & Components PDP of Adder Comparisons 38


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