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(U of Waterloo E&CE Fall) copyright © Mark Aagaard 2001 permission is granted to reproduce without modification Design Patterns University of Waterloo E&CE Fall Lec-03
(U of Waterloo E&CE Fall) copyright © Mark Aagaard 2001 permission is granted to reproduce without modification Storage: Dual-Port Memory Array Can read from two addresses at same time Can write to one address at a time Area: x that of single-port memory data_inA write_enA addrA data_outA addrB data_outB
(U of Waterloo E&CE Fall) copyright © Mark Aagaard 2001 permission is granted to reproduce without modification Concurrent State Machines Decompose a state machine into several machines operating concurrently (in parallel) Common decomposition is based on output signals Simplifies next-state equations Can increase performance and reduce area
(U of Waterloo E&CE Fall) copyright © Mark Aagaard 2001 permission is granted to reproduce without modification Datapath Design and Optimization University of Waterloo E&CE Fall Lec-04
(U of Waterloo E&CE Fall) copyright © Mark Aagaard 2001 permission is granted to reproduce without modification Design Comparison abc d + e + f z abc d + e + f z inputs outputs registers adders clock speed latency f0.5f 64
(U of Waterloo E&CE Fall) copyright © Mark Aagaard 2001 permission is granted to reproduce without modification From Dataflow to Hardware + Clean up the drawing, add the state machine z in3in2in1 abc de f r1 r2 r3 r2 out1 r3
(U of Waterloo E&CE Fall) copyright © Mark Aagaard 2001 permission is granted to reproduce without modification Datapath + Storage + Control + + datapath storage control The three main classes of hardware
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