7CPU has direct control over I/O Programmed I/OCPU has direct control over I/OSensing statusRead/write commandsTransferring dataCPU waits for I/O module to complete operationUsually not a good use of CPU time
8Programmed I/O - detail CPU requests I/O operationI/O module performs operationI/O module sets status bitsCPU checks status bits periodicallyCPU may wait or come back later
9Interrupt driven I/O - CPU Viewpoint Issue I/O commandDo other work- Check for interrupt at end of each instruction cycleWhen interrupt request is granted:-Save context (registers)Process interruptExecute “service routine”Continue other work
10Interrupt Driven I/O – Device Perspective CPU issues I/O command (enable interrupt)I/O module gets data from peripheral while CPU does other workI/O module interrupts CPU (Interrupt request)Device serviced by CPU
11DMA FunctionDMA controller(s) takes over from CPU for I/OAdditional Module(s) attached to bus
13CPU tells DMA controller:- DMA OperationCPU tells DMA controller:-Read/WriteDevice addressStarting address of memory block for dataAmount of data to be transferredCPU carries on with other workDMA controller deals with transferDMA controller sends interrupt when finished
14DMA Transfer Cycle Stealing DMA controller takes over bus for a cycleTransfer of one word of dataNot an interruptCPU does not switch contextCPU suspended just before it accesses busi.e. before an operand or data fetch or a data writeSlows down CPU but not as much as CPU doing transfer
15DMA and Interrupt Breakpoints During an Instruction Cycle What is wrong with this?
16AsideWhat effect does caching memory have on DMA?What effect does use of DRAMs have on DMA ?
17Single Bus, Detached DMA controller Each transfer uses bus twice DMA Configurations (1)Single Bus, Detached DMA controllerEach transfer uses bus twiceI/O to DMA then DMA to memoryCPU is suspended twice
18Single Bus, Integrated DMA controller DMA Configurations (2)Single Bus, Integrated DMA controllerController may support >1 deviceEach transfer uses bus onceDMA to memoryCPU is suspended once
19Bus supports all DMA enabled devices Each transfer uses bus once DMA Configurations (3)Separate I/O BusBus supports all DMA enabled devicesEach transfer uses bus onceDMA to memoryCPU is suspended once
20I/O channels are processors dedicated to I/O e.g. 3D graphics cards CPU instructs I/O controller to do transferI/O controller does entire transfer from one or many devicesMakes transfers less visible to CPUImproves speedTakes load off CPU
29Ethernet CSMA/CD (Carrier Sense Multiple Access/Collision Detection) A local area network access method in which contention between two or more stations is resolved by collision detection.When two stations transmit at the same time, they both stop and signal a collision has occurred. Each then tries again after waiting a predetermined time period. To avoid another collision, the stations involved each choose a random time interval to schedule the retransmission of the collided frame.To make sure that the collision is recognized, Ethernet requires that a station must continue transmitting until the 50 microsecond period has ended. If the station has less than 64 bytes of data to send, then it must pad the data by adding zeros at the end.
34Layering – Example: OSI Network Layers International Standards Organization’s (ISO) Open Systems Interconnection (ISO) Model:The Physical Layer describes the physical properties of the various communications media, as well as the electrical properties and interpretation of the exchanged signals.Example: this layer defines the size of Ethernet coaxial cable, the type of BNC connector used, and the termination method.The Data Link Layer describes the logical organization of data bits transmitted on a particular medium.Example: this layer defines the framing, addressing and check-summing of Ethernet packets.The Network Layer describes how a series of exchanges over various data links can deliver data between any two nodes in a network.Example: this layer defines the addressing and routing structure of the Internet.The Transport Layer describes the quality and nature of the data delivery.Example: this layer defines if and how retransmissions will be used to ensure data delivery.The Session Layer describes the organization of data sequences larger than the packets handled by lower layers.Example: this layer describes how request and reply packets are paired in a remote procedure call.The Presentation Layer describes the syntax of data being transferred.Example: this layer describes how floating point numbers can be exchanged between hosts with different math formats.The Application Layer describes how real work actually gets done.Example: this layer would implement file system operations.
35Simple Example OF 7 Layer OSI Model Application Layer: Set of C Instructions, Set of DataI0 I1 I2 …. IN Do D1 D2 … DmPresentation Layer: ASCII CodingASC I0 I1 I2 …. IN Do D1 D2 … DmSession Layer: What process at computer x is communicating with what process at computer yX4 Y6 ASC I0 I1 I2 …. IN Do D1 D2 … DmTransport Layer: Guaranteed Transmission, sequentially numbered packets of 4096 bytesGT4 P34 x4 Y6 ASC I0 I1 I2 …. IN Do D1 D2 … Dm PCKSUMNetwork Layer: Path through NetworkN23 N3 N53 GT P34 x4 Y6 ASC I0 I1 I2 …. IN Do D1 D2 … Dm PCKSUMData Link Layer: Serial 256 bytes per frameSTRT T(N23 N3 N53 GT P34 x4 Y6 ASC I0 I1 I2 …. IN Do D1 D2 … Dm PCKSUM)CKSMPhysical Layer: 9600Baud, Coax cable
36IEEE 1394 FireWire (Competitor to USB) High performance serial busFastLow costEasy to implementAlso being used in digital cameras, VCRs and TV
37FireWire Configuration Daisy chainUp to 63 devices on single portReally 64 of which one is the interface itselfUp to 1022 buses can be connected with bridgesAutomatic configurationNo bus terminatorsMay be tree structure
41FireWire - Physical Layer Data rates from 25 to 400MbpsTwo forms of arbitrationBased on tree structureRoot acts as arbiterFirst come first servedNatural priority controls simultaneous requestsi.e. who is nearest to rootFair arbitrationUrgent arbitration
42Two transmission types FireWire - Link LayerTwo transmission typesAsynchronousVariable amount of data and several bytes of transaction data transferred as a packetTo explicit addressAcknowledgement returnedIsochronousVariable amount of data in sequence of fixed size packets at regular intervalsSimplified addressingNo acknowledgement
44I/O specification aimed at high end servers InfiniBandI/O specification aimed at high end serversMerger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel)Version 1 released early 2001Architecture and spec. for data flow between processor and intelligent I/O devicesIntended to replace PCI in serversIncreased capacity, expandability, flexibility
45InfiniBand Architecture Remote storage, networking and connection between serversAttach servers, remote storage, network devices to central fabric of switches and linksGreater server densityScalable data centreIndependent nodes added as requiredI/O distance from server up to17m using copper300m multimode fibre optic10km single mode fibreUp to 30Gbps
47InfiniBand Operation16 logical channels (virtual lanes) per physical linkOne lane for management, rest for dataData in stream of packetsVirtual lane dedicated temporarily to end to end transferSwitch maps traffic from incoming to outgoing lane