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Chapter 7 Input/Output HW: 7:13 & 7:18 Due Wed, 11/8/06.

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Presentation on theme: "Chapter 7 Input/Output HW: 7:13 & 7:18 Due Wed, 11/8/06."— Presentation transcript:

1 Chapter 7 Input/Output HW: 7:13 & 7:18 Due Wed, 11/8/06

2 Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower than CPU and RAM Need I/O modules

3 Generic Model of I/O Module

4 I/O Module Function Support single or multiple devices Hide or reveal device properties Provides: Control & Timing CPU Communication Device Communication Data Buffering Error Detection

5 I/O Module Diagram

6 Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA)

7 Programmed I/O CPU has direct control over I/O —Sensing status —Read/write commands —Transferring data CPU waits for I/O module to complete operation Usually not a good use of CPU time

8 Programmed I/O - detail CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically CPU may wait or come back later

9 Interrupt driven I/O - CPU Viewpoint Issue I/O command Do other work - Check for interrupt at end of each instruction cycle When interrupt request is granted:- —Save context (registers) —Process interrupt –Execute “service routine” Continue other work

10 Interrupt Driven I/O – Device Perspective CPU issues I/O command (enable interrupt) I/O module gets data from peripheral while CPU does other work I/O module interrupts CPU (Interrupt request) Device serviced by CPU

11 DMA Function DMA controller(s) takes over from CPU for I/O Additional Module(s) attached to bus

12 Typical DMA Module Diagram

13 DMA Operation CPU tells DMA controller:- —Read/Write —Device address —Starting address of memory block for data —Amount of data to be transferred CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished

14 DMA Transfer Cycle Stealing DMA controller takes over bus for a cycle Transfer of one word of data Not an interrupt —CPU does not switch context CPU suspended just before it accesses bus —i.e. before an operand or data fetch or a data write Slows down CPU but not as much as CPU doing transfer

15 DMA and Interrupt Breakpoints During an Instruction Cycle What is wrong with this?

16 Aside What effect does caching memory have on DMA? What effect does use of DRAMs have on DMA ?

17 DMA Configurations (1) Single Bus, Detached DMA controller Each transfer uses bus twice —I/O to DMA then DMA to memory CPU is suspended twice

18 DMA Configurations (2) Single Bus, Integrated DMA controller Controller may support >1 device Each transfer uses bus once —DMA to memory CPU is suspended once

19 DMA Configurations (3) Separate I/O Bus Bus supports all DMA enabled devices Each transfer uses bus once —DMA to memory CPU is suspended once

20 I/O Channels I/O channels are processors dedicated to I/O e.g. 3D graphics cards CPU instructs I/O controller to do transfer I/O controller does entire transfer from one or many devices Makes transfers less visible to CPU Improves speed —Takes load off CPU

21 I/O Channel Architecture

22 Interfacing Options Parallel - PCI - SCSI Serial - RS 232 Local Networks - Ethernet Newer technologies - FireWire - InfiniBand - USB Wireless - BlueTooth - WiFi Automation - CAN

23 Intel 82C55A Programmable Peripheral Interface

24 Keyboard/Display Interfaces to 82C55A

25 Serial - RS 232 UART (Universal Asynchronous Receiver & Transmitter) Serial interface on a chip Historically very significant After 30 years, still a standard

26 RS232 Character transmission

27 UART Block Diagram

28 UART Application

29 Ethernet CSMA/CD (Carrier Sense Multiple Access/Collision Detection) A local area network access method in which contention between two or more stations is resolved by collision detection. When two stations transmit at the same time, they both stop and signal a collision has occurred. Each then tries again after waiting a predetermined time period. To avoid another collision, the stations involved each choose a random time interval to schedule the retransmission of the collided frame. To make sure that the collision is recognized, Ethernet requires that a station must continue transmitting until the 50 microsecond period has ended. If the station has less than 64 bytes of data to send, then it must pad the data by adding zeros at the end.

30 Bob Metcalf’s Ethernet Concept - 1976

31 Network Reference model - Ethernet

32 Ethernet packet

33 Ethernet block diagram

34 Layering – Example: OSI Network Layers The Physical Layer describes the physical properties of the various communications media, as well as the electrical properties and interpretation of the exchanged signals. Example: this layer defines the size of Ethernet coaxial cable, the type of BNC connector used, and the termination method. The Data Link Layer describes the logical organization of data bits transmitted on a particular medium. Example: this layer defines the framing, addressing and check-summing of Ethernet packets. The Network Layer describes how a series of exchanges over various data links can deliver data between any two nodes in a network. Example: this layer defines the addressing and routing structure of the Internet. The Transport Layer describes the quality and nature of the data delivery. Example: this layer defines if and how retransmissions will be used to ensure data delivery. The Session Layer describes the organization of data sequences larger than the packets handled by lower layers. Example: this layer describes how request and reply packets are paired in a remote procedure call. The Presentation Layer describes the syntax of data being transferred. Example: this layer describes how floating point numbers can be exchanged between hosts with different math formats. The Application Layer describes how real work actually gets done. Example: this layer would implement file system operations. International Standards Organization’s (ISO) Open Systems Interconnection (ISO) Model:

35 Simple Example OF 7 Layer OSI Model Application Layer: Set of C Instructions, Set of Data I0 I1 I2 …. IN Do D1 D2 … Dm Presentation Layer: ASCII Coding ASC I0 I1 I2 …. IN Do D1 D2 … Dm Session Layer: What process at computer x is communicating with what process at computer y X4 Y6 ASC I0 I1 I2 …. IN Do D1 D2 … Dm Transport Layer: Guaranteed Transmission, sequentially numbered packets of 4096 bytes GT4 P34 x4 Y6 ASC I0 I1 I2 …. IN Do D1 D2 … Dm PCKSUM Network Layer: Path through Network N23 N3 N53 GT P34 x4 Y6 ASC I0 I1 I2 …. IN Do D1 D2 … Dm PCKSUM Data Link Layer: Serial 256 bytes per frame STRT T(N23 N3 N53 GT P34 x4 Y6 ASC I0 I1 I2 …. IN Do D1 D2 … Dm PCKSUM)CKSM Physical Layer: 9600Baud, Coax cable

36 IEEE 1394 FireWire (Competitor to USB) High performance serial bus Fast Low cost Easy to implement Also being used in digital cameras, VCRs and TV

37 FireWire Configuration Daisy chain Up to 63 devices on single port —Really 64 of which one is the interface itself Up to 1022 buses can be connected with bridges Automatic configuration No bus terminators May be tree structure

38 Simple FireWire Configuration

39 FireWire 3 Layer Stack Physical —Transmission medium, electrical and signaling characteristics Link —Transmission of data in packets Transaction —Request-response protocol

40 FireWire Protocol Stack

41 FireWire - Physical Layer Data rates from 25 to 400Mbps Two forms of arbitration —Based on tree structure —Root acts as arbiter —First come first served —Natural priority controls simultaneous requests –i.e. who is nearest to root —Fair arbitration —Urgent arbitration

42 FireWire - Link Layer Two transmission types —Asynchronous –Variable amount of data and several bytes of transaction data transferred as a packet –To explicit address –Acknowledgement returned —Isochronous –Variable amount of data in sequence of fixed size packets at regular intervals –Simplified addressing –No acknowledgement

43 FireWire Subactions

44 InfiniBand I/O specification aimed at high end servers —Merger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel) Version 1 released early 2001 Architecture and spec. for data flow between processor and intelligent I/O devices Intended to replace PCI in servers Increased capacity, expandability, flexibility

45 InfiniBand Architecture Remote storage, networking and connection between servers Attach servers, remote storage, network devices to central fabric of switches and links Greater server density Scalable data centre Independent nodes added as required I/O distance from server up to —17m using copper —300m multimode fibre optic —10km single mode fibre Up to 30Gbps

46 InfiniBand Switch Fabric

47 InfiniBand Operation 16 logical channels (virtual lanes) per physical link One lane for management, rest for data Data in stream of packets Virtual lane dedicated temporarily to end to end transfer Switch maps traffic from incoming to outgoing lane

48 InfiniBand Protocol Stack


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