2 I/O key pointsI/O architecture is computer’s interface to the outside world.It provides the OS with the information it needs to manage I/O activity effectively.There are 3 major I/O techniques:Programmed I/OInterrupt-Driven I/ODirect Memory Access (DMA)Two important examples of external I/O interfaces areFireWireInfiniBand
3 Input/Output Problems Wide variety of peripherals with various methods of operation.Is it practical to incorporate the necessary logic within the cpu to control a range of devices?_Delivering different amounts of data(Peripheral/memory speed. Communication with peripheral – high speed bus). Is peripheral faster than memory? Can it be?At different speedsIn different formats (word lengths). Hence needAll slower than CPU and RAMNeed I/O modules
4 Generic Model of I/O Module Model has 2 functionsInterface to CPU and MemoryInterface to one or more peripheralsExternal devices exchange data between the external environment and the computer.The link is used to exchange control, status and data between the I/O module and external device (Peripheral device).
5 We classify External Devices into 3 categories Human readable (comms with computer user)Screen, printer, keyboardMachine readable (comms with equipment)Monitoring and control. Is a magnetic disk…?Communication (comms with remote devices)ModemNetwork Interface Card (NIC)
6 External Device Block Diagram The interface to the I/O module is in the form of control, data and status signals.Control signals determine the function that the device will perform, e.g. Send data to the I/O module (INPUT or READ), accept data from I/O (OUTPUR or WRITE).Status signals indicate the state of the device. E.g. READY/NOT READY (for transferring data).Control logic associated with the device, controls the device’s operation in response to direction from the I/O module.Transducer converts data from electrical to other forms of energy during output and from other forms to electrical during input.
7 Data Buffering – Transfer rate of data into and out of I/O… I/O Module Function- The major functions or requirements for an I/O module fall into the following categories:Control & Timing (to coordinate the flow of traffic between internal resources and external devices) – See examples in next slide…CPU Communication (Command decoding, data, status reporting e.g. BUSY/READY, address recognition).Device CommunicationData Buffering – Transfer rate of data into and out of I/O…Error Detection – Mechanical or electrical?...e.g. paper jam
8 CPU checks I/O module device status I/O module returns status I/O StepsExample: the control of transfer of data from an external device to the cpu might involve the following sequence of steps:CPU checks I/O module device statusI/O module returns statusIf ready, CPU requests data transferI/O module gets data (bits) from deviceI/O module transfers data to CPUVariations for output, DMA, etc.
10 Hide or reveal device properties to CPU I/O Module DecisionsHide or reveal device properties to CPUSupport multiple or single deviceControl device functions or leave for CPUAlso O/S decisionse.g. Unix treats everything it can as a file
11 Input Output Techniques ProgrammedI/O occurs under the direct and continuous control of the program requesting the I/O operation. Data are exchanged between the cpu and the I/O module.Interrupt drivenA program issues an I/O command and then continues to execute, until it is interrupted by the I/O hardware to signal the end of the I/O operation.Direct Memory Access (DMA)A specialized I/O processor takes over control of an I/O operation to move a large block of data. The I/O module and main memory exchange data directly, without any involvement of processor.
12 Three Techniques for Input of a Block of Data There are 4 types of I/O commands:ControlTestReadWrite
13 CPU has direct control over I/O Programmed I/OCPU has direct control over I/OSensing statusRead/write commandsTransferring dataCPU waits for I/O module to complete operationWastes CPU time
14 Programmed I/O - detail CPU requests I/O operationI/O module performs operationI/O module sets status bitsCPU checks status bits periodicallyI/O module does not inform CPU directlyI/O module does not interrupt CPUCPU may wait or come back later
15 I/O Commands CPU issues address CPU issues command Identifies module (& device if >1 per module)CPU issues commandControl - telling module what to doe.g. spin up diskTest - check statuse.g. power? Error?Read/WriteModule transfers data via buffer from/to device
16 Addressing I/O Devices Under programmed I/O data transfer is very like memory access (CPU viewpoint)Each device given unique identifierCPU commands contain identifier (address)
17 I/O Mapping Memory mapped I/O Isolated I/O When the processor, main memory and I/O share a common bus, two modes of addressing are possible.Memory mapped I/ODevices and memory share an address spaceI/O looks just like memory read/writeNo special commands for I/OLarge selection of memory access commands availableIsolated I/OSeparate address spacesNeed I/O or memory select linesSpecial commands for I/OLimited set
18 Memory Mapped and Isolated I/O Assume a 10-bit address, with a 512-bit memory (locations 0-511) and up to 512 I/O addresses (locations ). Two addresses are dedicated to keyboard input from a particular terminal. Address 516 refers to the data register and address 517 refers to the status register, which also functions as a control register for receiving processor commands. The program shown will read 1 byte of data from the keyboard into an accumulator register in the processor.With isolated I/O the I/O ports are accessible only by special I/O commands, which activate the I/O command lines on the bus.
19 Interrupt Driven I/OOvercomes CPU waitingNo repeated CPU checking of deviceI/O module interrupts when ready
20 Interrupt Driven I/O Basic Operation CPU issues read commandI/O module gets data from peripheral whilst CPU does other workI/O module interrupts CPUCPU requests dataI/O module transfers data
22 Check for interrupt at end of each instruction cycle If interrupted:- CPU ViewpointIssue read commandDo other workCheck for interrupt at end of each instruction cycleIf interrupted:-Save context (registers)Process interruptFetch data & storeSee Operating Systems notes
23 Changes in Memory and Registers for an Interrupt
24 How do you identify the module issuing the interrupt? Design IssuesHow do you identify the module issuing the interrupt?How do you deal with multiple interrupts?i.e. an interrupt handler being interrupted
25 Identifying Interrupting Module (1) Different line for each modulePCLimits number of devicesSoftware pollCPU asks each module in turnSlow
26 Identifying Interrupting Module (2) Daisy Chain or Hardware pollInterrupt Acknowledge sent down a chainModule responsible places vector on busCPU uses vector to identify handler routineBus MasterModule must claim the bus before it can raise interrupte.g. PCI & SCSI
27 Multiple InterruptsEach interrupt line has a priorityHigher priority lines can interrupt lower priority linesIf bus mastering only current master can interrupt
28 Example - PC Bus80x86 has one interrupt line8086 based systems use one 8259A interrupt controller8259A has 8 interrupt lines
29 Sequence of Events8259A accepts interrupts8259A determines priority8259A signals 8086 (raises INTR line)CPU Acknowledges8259A puts correct vector on data busCPU processes interrupt
30 ISA Bus Interrupt System ISA bus chains two 8259As togetherLink is via interrupt 2Gives 15 lines16 lines less one for linkIRQ 9 is used to re-route anything trying to use IRQ 2Backwards compatibilityIncorporated in chip set
34 Interrupt driven and programmed I/O require active CPU intervention Direct Memory AccessInterrupt driven and programmed I/O require active CPU interventionTransfer rate is limitedCPU is tied upDMA is the answer
35 DMA FunctionAdditional Module (hardware) on busDMA controller takes over from CPU for I/O
37 CPU tells DMA controller:- DMA OperationCPU tells DMA controller:-Read/WriteDevice addressStarting address of memory block for dataAmount of data to be transferredCPU carries on with other workDMA controller deals with transferDMA controller sends interrupt when finished
38 DMA Transfer Cycle Stealing DMA controller takes over bus for a cycleTransfer of one word of dataNot an interruptCPU does not switch contextCPU suspended just before it accesses busi.e. before an operand or data fetch or a data writeSlows down CPU but not as much as CPU doing transfer
39 DMA and Interrupt Breakpoints During an Instruction Cycle
40 AsideWhat effect does caching memory have on DMA?What about on board cache?Hint: how much are the system buses available?
41 Single Bus, Detached DMA controller Each transfer uses bus twice DMA Configurations (1)Single Bus, Detached DMA controllerEach transfer uses bus twiceI/O to DMA then DMA to memoryCPU is suspended twice
42 Single Bus, Integrated DMA controller DMA Configurations (2)Single Bus, Integrated DMA controllerController may support >1 deviceEach transfer uses bus onceDMA to memoryCPU is suspended once
43 Bus supports all DMA enabled devices Each transfer uses bus once DMA Configurations (3)Separate I/O BusBus supports all DMA enabled devicesEach transfer uses bus onceDMA to memoryCPU is suspended once
44 Intel 8237A DMA Controller Interfaces to 80x86 family and DRAM When DMA module needs buses it sends HOLD signal to processorCPU responds HLDA (hold acknowledge)DMA module can use busesE.g. transfer data from memory to diskDevice requests service of DMA by pulling DREQ (DMA request) highDMA puts high on HRQ (hold request),CPU finishes present bus cycle (not necessarily present instruction) and puts high on HDLA (hold acknowledge). HOLD remains active for duration of DMADMA activates DACK (DMA acknowledge), telling device to start transferDMA starts transfer by putting address of first byte on address bus and activating MEMR; it then activates IOW to write to peripheral. DMA decrements counter and increments address pointer. Repeat until count reaches zeroDMA deactivates HRQ, giving bus back to CPU
46 While DMA using buses processor idle Processor using bus, DMA idle Fly-ByWhile DMA using buses processor idleProcessor using bus, DMA idleKnown as fly-by DMA controllerData does not pass through and is not stored in DMA chipDMA only between I/O port and memoryNot between two I/O ports or two memory locationsCan do memory to memory via register8237 contains four DMA channelsProgrammed independentlyAny one activeNumbered 0, 1, 2, and 3
47 I/O devices getting more sophisticated e.g. 3D graphics cards I/O ChannelsI/O devices getting more sophisticatede.g. 3D graphics cardsCPU instructs I/O controller to do transferI/O controller does entire transferImproves speedTakes load off CPUDedicated processor is faster
49 InterfacingConnecting devices togetherBit of wire?Dedicated processor/memory/buses?E.g. FireWire, InfiniBand
50 IEEE 1394 FireWireHigh performance serial busFastLow costEasy to implementAlso being used in digital cameras, VCRs and TV
51 FireWire Configuration Daisy chainUp to 63 devices on single portReally 64 of which one is the interface itselfUp to 1022 buses can be connected with bridgesAutomatic configurationNo bus terminatorsMay be tree structure
55 FireWire - Physical Layer Data rates from 25 to 400MbpsTwo forms of arbitrationBased on tree structureRoot acts as arbiterFirst come first servedNatural priority controls simultaneous requestsi.e. who is nearest to rootFair arbitrationUrgent arbitration
56 Two transmission types FireWire - Link LayerTwo transmission typesAsynchronousVariable amount of data and several bytes of transaction data transferred as a packetTo explicit addressAcknowledgement returnedIsochronousVariable amount of data in sequence of fixed size packets at regular intervalsSimplified addressingNo acknowledgement
58 I/O specification aimed at high end servers InfiniBandI/O specification aimed at high end serversMerger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel)Version 1 released early 2001Architecture and spec. for data flow between processor and intelligent I/O devicesIntended to replace PCI in serversIncreased capacity, expandability, flexibility
59 InfiniBand Architecture Remote storage, networking and connection between serversAttach servers, remote storage, network devices to central fabric of switches and linksGreater server densityScalable data centreIndependent nodes added as requiredI/O distance from server up to17m using copper300m multimode fibre optic10km single mode fibreUp to 30Gbps
61 InfiniBand Operation16 logical channels (virtual lanes) per physical linkOne lane for management, rest for dataData in stream of packetsVirtual lane dedicated temporarily to end to end transferSwitch maps traffic from incoming to outgoing lane