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Computer Buses For many of you who have depopulated his/her breadboards, THANKS! There are still some to be depopulated. Please dont forget to do it this.

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Presentation on theme: "Computer Buses For many of you who have depopulated his/her breadboards, THANKS! There are still some to be depopulated. Please dont forget to do it this."— Presentation transcript:

1 Computer Buses For many of you who have depopulated his/her breadboards, THANKS! There are still some to be depopulated. Please dont forget to do it this week, please.

2 Final Exam – Thur, Dec 11, 4:15-6:20 Logic, Flip Flops, Timing, Synchronous / Asynchronous Circuits, Memory Organization, Finite State Machines (FSM) RISC / CISC Computers, MIPS Organization, MIPS Instructions, MIPS Addressing, MIPS Frames / Context Switching, MIPS Assembly/Machine Programming (will have MIPS card) Hamming Code Developing MIPS Datapaths, MIPS FSM Implementations, and Alternative Microprogramming Midterm Pipelining - implementing, forwarding, handling branches Cache – Direct, Associative, Set Associative Virtual memory – Organization, Page Faults, and Look Aside Buffer IA-64 - Bundled Instructions /explicit parallel, predicated execution, control speculation, speculative data loading, software pipelining / unraveling loops (dont expect you to know details of the IA-64) I/O Devices & Buses – Magnetic Disks, Solid State Disks, Flash Memory, Optical Disks, Magnetic Tape - Organization, Implementation, Interrupts, Bus Control, DMA 60% on material covered after the midterm

3 Basic I/O System Example Processor Cache Memory - I/O Bus Main Memory I/O Controller Disk … I/O Controller Disk …

4 Computer Buses The bus is a critical component of the Computer: l They are shared components that provide the paths for all parts of the computer to communicate with each other l They can reduce the complexity of communications between computer components l They contain conduits for data, addressing, and timing/control l They need a protocol that all users use l They can provide an easy way to evolve a computer system – add components l They can be a serious bottleneck if not designed and used appropriately l As systems grow, they need to evolve hierarchically l They can be parallel or serial l They can have data widths larger than the computer word length

5 Types of Buses Processor-memory bus (maybe proprietary) l Short and high speed l Matched to the memory system to maximize the memory- processor bandwidth l Optimized for cache block transfers Backplane bus (maybe industry standard) l The backplane is an interconnection structure within the chassis l Used as an intermediary bus connecting I/O busses to the processor-memory bus I/O bus (industry standard, e.g., SCSI, PCI,USB, Firewire) l Usually is lengthy and slower l Needs to accommodate a wide range of I/O devices l Connects to the processor-memory bus or backplane bus

6 Bus Characteristics Data & Address lines l Data, addresses, and complex commands Control lines l Signal requests and acknowledgments l Indicate what type of information is on the data lines Bus transaction consists of l Master issuing the command (and address) – request l Slave receiving (or sending) the data – action l Defined by what the transaction does to memory -Input – inputs data from the I/O device to the memory -Output – outputs data from the memory to the I/O device Bus Master Bus Slave Control lines: Master initiates requests Data lines: Data can go either way

7 Buses What are the Bus design considerations? l Accessibility l Speed l Reliability l Extensibility l Bottle necks l Noise (electrical) l Flexibility l Ease of Interfacing l Power l Sharability l Communication Protocol l Length Should Buses distribute Power?

8 Computer Bus Buses are composed of three sets of lines Not all devices will use all lines in each category

9 What does this improve?

10 What is gained here?

11 Where are the challenges here?

12 How about this one?

13 Selector and Multiplexor Channels

14 Parallel and Serial I/O

15 Daisy Chained Bus

16 USB Topology

17 Computer Bus Control lines include: Clock(s) Interrupt Support Bus Control R/W etc.

18 Bus Communications Bus Protocols l Asynchronous l Synchronous l Memory Read / Writes ? l I/O Read Writes? l Peer communication – e.g. CPU to CPU l Are communications verified? l Is there error checking ?

19 Synchronous and Asynchronous Buses Synchronous bus (e.g., processor-memory buses) l Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clock l Advantage: involves very little logic and can run very fast l Disadvantages: -Every device communicating on the bus must use same clock rate -To avoid clock skew, they cannot be long if they are fast Asynchronous bus (e.g., I/O buses) l It is not clocked, so requires a handshaking protocol and additional control lines (ReadReq, Ack, DataRdy) l Advantages: -Can accommodate a wide range of devices and device speeds -Can be lengthened without worrying about clock skew or synchronization problems l Disadvantage: slow(er)

20 Synchronous Bus

21 Asynchronous Bus Handshaking Protocol 7. I/O device sees DataRdy go low and drops Ack Output (read) data from memory to an I/O device I/O device signals a request by raising ReadReq and putting the addr on the data lines ReadReq Data Ack DataRdy addrdata Memory sees ReadReq, reads addr from data lines, and raises Ack 2. I/O device sees Ack and releases the ReadReq and data lines 3. Memory sees ReadReq go low and drops Ack 4. When memory has data ready, it places it on data lines and raises DataRdy 5. I/O device sees DataRdy, reads the data from data lines, and raises Ack 6. Memory sees Ack, releases the data lines, and drops DataRdy

22 Asynchronous Bus

23 Physical Considerations How are the various components connected? l Unidirectional / bidirectional l And /Or combinational circuits l Wired Or circuits l Tri-state

24 Or configuration: Normal Gate Output Stage: Observe that the output is always driven High or low. What happens if we connect two of these to the bus?

25 Wired OR Now any new device can just be connected to the bus anywhere. If no device is pulling the bus line low, it is high A NOR function

26 Tri-State Now each device can either drive the line high, drive it low, or leave it open

27 Symbols Buffer Open Collector Tri-State

28 Signal Considerations What about signal integrity? l Fanout What about noise? l Drivers What about length limitations? l Bus termination

29 Characteristic Impedance Terminated at Char Impedance Not Terminated at Char Impedance

30 Termination comparisons Open Termination Short Termination Proper Termination

31 A Typical I/O System Processor Cache Memory - I/O Bus Main Memory I/O Controller Disk I/O Controller I/O Controller Graphics Network Interrupts Disk

32 Interrupt Systems Interrupt Systems Allow Devices to request I/O Service when THEY are ready Process? l Device given permission to generate an Interrupt Request l Request an Interrupt of the present process (IF priority allows) l On Request Acknowledge, provide Vector of Service Routine (just like a memory read) l CPU makes a context switch and begins the Service Routine l On completion of the service, a context switchback occurs l The original process continues where it left off

33 Bus Master A bus Master controls the bus l Reads l Writes l Interrupt Request / Acknowledge l Bus Master Request / Acknowledge Why would there be multiple potential Bus Masters? l Multiple Processor Shared Systems l One Processor can use the bus while another is doing internal processing l To accommodate the replacement of a bad bus master l Sometimes there is a voting system to determine Bus Control l Allows I/O devices to talk to memory or another I/O Device without using the processor time

34 Bus Master How does a Bus Master System work? l A potential Bus Master can Request the Bus Control l On Acknowledgement / Grant the new Master Takes Control l When there is a timeout due to no bus activity l A Potential Bus Controller announces intention to take control l Unless there is an objection, it then takes Control l If there are multiple requests l There is an arbitration process to determine who takes control

35 DMA (Direct memory Access) Is there some way to use the bus when the master is not using it? l Yes, its called a DMA l To use the Bus, a device must request to DMA l On Grant, the device can make multiple transfers and then give up the Bus. During this time the Bus Master doesnt use the Bus (possibly goes to sleep) How is it used? l Typically, a device, like a Disk, requests the right to DMA one word or a Block of Words to a memory page. l When granted, the Disk fills the Block – in a burst (while the Bus Master perhaps sleeps) or one word at a time when the bus is not busy. l When the Block has been transferred, the Device may likely Interrupt the CPU to report the transaction is completed.

36 Some DMA Configurations

37 The Need for Bus Arbitration Multiple devices may need to use the bus at the same time so must have a way to arbitrate multiple requests Bus arbitration schemes usually try to balance: l Bus priority – the highest priority device should be serviced first l Fairness – even the lowest priority device should never be completely locked out from the bus Bus arbitration schemes can be divided into four classes l Daisy chain arbitration – see next slide l Centralized, parallel arbitration – see next-next slide l Distributed arbitration by self-selection – each device wanting the bus places a code indicating its identity on the bus l Distributed arbitration by collision detection – device uses the bus when its not busy and if a collision happens (because some other device also decides to use the bus) then the device tries again later (Ethernet)

38 Daisy Chain Bus Arbitration Advantage: simple Disadvantages: l Cannot assure fairness – a low-priority device may be locked out indefinitely l Slower – the daisy chain grant signal limits the bus speed Bus Arbiter Device 1 Highest Priority Device N Lowest Priority Device 2 Ack Release Request wired-OR Data/Addr

39 Centralized Parallel Arbitration Advantages: flexible, can assure fairness Disadvantages: more complicated arbiter hardware Used in essentially all processor-memory buses and in high-speed I/O buses Bus Arbiter Device 1 Device NDevice 2 Ack1 Data/Addr Ack2 AckN Request1Request2RequestN

40 Layering – Example: OSI Network Layers The Physical Layer describes the physical properties of the various communications media, as well as the electrical properties and interpretation of the exchanged signals. Example: this layer defines the size of Ethernet coaxial cable, the type of BNC connector used, and the termination method. The Data Link Layer describes the logical organization of data bits transmitted on a particular medium. Example: this layer defines the framing, addressing and check-summing of Ethernet packets. The Network Layer describes how a series of exchanges over various data links can deliver data between any two nodes in a network. Example: this layer defines the addressing and routing structure of the Internet. The Transport Layer describes the quality and nature of the data delivery. Example: this layer defines if and how retransmissions will be used to ensure data delivery. The Session Layer describes the organization of data sequences larger than the packets handled by lower layers. Example: this layer describes how request and reply packets are paired in a remote procedure call. The Presentation Layer describes the syntax of data being transferred. Example: this layer describes how floating point numbers can be exchanged between hosts with different math formats. The Application Layer describes how real work actually gets done. Example: this layer would implement file system operations. International Standards Organizations (ISO) Open Systems Interconnection (ISO) Model:

41 Simple Example OF 7 Layer OSI Model Application Layer: Set of C Instructions, Set of Data {I0 I1 I2 …. IN Do D1 D2 … Dm} Presentation Layer: ASCII Coding {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}} Session Layer: What process at computer x is communicating with what process at computer y {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} Transport Layer: Guaranteed Transmission, sequentially numbered packets of 4096 bytes {GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} PCKSUM} Network Layer: Path through Network {N23 N3 N53 {GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} PCKSUM}} Data Link Layer: Serial 256 bytes per frame {STRT T{N23 N3 N53 {GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} PCKSUM}}CHKSM} Physical Layer: 9600Baud, Coax cable - {Start {….}Parity Stop Stop}

42 Ethernet packet

43 Bob Metcalfs Ethernet Concept

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