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Introduction Purpose  To introduce Fox Electronics XpressO Oscillator Technology Objective  Showcase XpressO’s cutting edge Technology and how it can.

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Presentation on theme: "Introduction Purpose  To introduce Fox Electronics XpressO Oscillator Technology Objective  Showcase XpressO’s cutting edge Technology and how it can."— Presentation transcript:

1 Introduction Purpose  To introduce Fox Electronics XpressO Oscillator Technology Objective  Showcase XpressO’s cutting edge Technology and how it can solve all of your Oscillator & VCXO timing requirements with superior performance, Reduced cost and lead times measured in days not months. Content  10 Slides Learning time  7 Approximately Minutes

2 750 kHz to 1.35 GHz 2.5V / 3.3V Operation Available Stabilities of 20 / 25 / 50 / 100 ppm available 0 to +70C / -40 to +85C Temperature options HCMOS / LV-PECL / LVDS outputs available Industry standard footprints Low jitter for Ethernet, SONET, Fiber Channel, etc. XO and VCXO Versions 7 x 5 mm 3.2 x 2.5 mm 5 x 3.2 mm

3 Low Cost - Approximately 20% to 50% less “cost” than a conventional oscillator equivalent Fast Delivery - Samples shipped next working day, production quantities shipped in 2 to 10 working days Low Jitter - Substantially lower jitter & phase noise than Programmable Oscillators and comparable to Fixed Frequency Oscillators

4 Established semiconductor group –Began development of custom programmable PLL and custom memory structure technologies 1998 – JITO – Focused on fast delivery –Oscillator utilizing the programmable PLL and custom memory structure –Patented frequency tuning allowing for tight accuracy –Streamlined manufacturing processes –10 day Just in Time delivery method developed 2003 – rfXO – Focused on low noise / high performance –High frequency (600MHz~1.25GHz) oscillator utilizing a low noise PLL is released for the SONET market –Stand-alone patented memory structure developed 2007 – XpressO tm – Combining low noise & fast delivery with low cost –Low noise Fractional-N PLL –Patented memory structure –3 rd Order DSM noise dispersion technology with selectable settings based on customer noise requirements –Streamlined raw material and manufacturing process

5 Utilizes multiple custom designed ASICs –Our own non-volatile memory structures – Lowers Cost –Noise-reducing DSM technology – Lowers Jitter and Phase noise –Building block architecture – Allows Fast Delivery –Different functional blocks – Provides Maximum Flexibility 6 U.S. and 8 foreign patents issued

6 H = HCMOS L = LVDS P = LVPECL M = LVDS (pin 2 E/D) Q = LVPECL (pin 2 E/D) X = HCMOS (comp 2 nd Output) 0 = ± 100 PPM 5 = ± 50 PPM 6 = ± 25 PPM 8 = ± 20 PPM (-20 ~ +70°C) 7 = 7 x 5mm 5 = 5 x 3.2mm 3 = 3.2 x 2.5mm C = Ceramic blank = -20°C to +70°C R = -40°C to +85°C 3 = 3.3 V 2 = 2.5 V F X O – H C R – Frequency (in MHz) Resolutions to 6 places past the decimal point H = HCMOS L = LVDS P = LVPECL X = HCMOS (comp 2 nd Output) B = ±50ppm Absolute Pull Range 7 = 7 x 5mm 5 = 5 x 3.2mm C = Ceramic 3 = 3.3 V F V X O – H C 5 3 B R – Frequency (in MHz) Resolutions to 6 places past the decimal point blank = -20°C to +70°C R = -40°C to +85°C XO Model Selection Guide VCXO Model Selection Guide

7 OutputFrequencyPhase Jitter 12kHz~20MHz RMS Period Jitter P-P Period Jitter RMS TIE Jitter Random Jitter (Rj) Deterministic Jitter (Dj) Total Jitter (14*Rj+Dj) HCMOS62.5MHz0.72 pS3.5 pS26.2 pS3.7 pS0.923 pS7.4 pS20.4 pS HCMOS106.25MHz0.77 pS4.5 pS31.2 pS3.6 pS0.999 pS7.7 pS21.7 pS HCMOS125MHz0.63 pS3.3 pS21.9 pS2.8 pS0.832 pS7.5 pS19.1 pS HCMOS156.25MHz0.75 pS4.1 pS29.7 pS3.3 pS0.911 pS7.6 pS20.4 pS LV-PECL62.5MHz0.76 pS2.5 pS18.4 pS2.7 pS0.790 pS7.7 pS18.7 pS LV-PECL155.52MHz0.73 pS3.9 pS29.1 pS3.5 pS1.348 pS9.86 pS28.7 pS LV-PECL212.5MHz0.69 pS5.96 pS38.4 pS3.8 pS1.220 pS9.26 pS26.3 pS LVDS106.25MHz0.76 pS4.7 pS33.8 pS3.5 pS0.7 pS7.1 pS17.2 pS LVDS156.25MHz0.74 pS3.0 pS17.6 pS3.6 pS1.3 pS5.8 pS23.6 pS LVDS212.5MHz0.63 pS5.8 pS37.0 pS3.9 pS0.9 pS6.7 pS18.7 pS LVDS MHz0.41 pS4.1 pS29.8 pS3.2 pS1.1 pS5.3 pS20.7 pS Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; VDD = 3.3V. TIE, Rj and Dj were measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; VDD = 3.3V. Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)

8 Serial Identification (Unique to every PART) Lot Identification (Unique to every ORDER) Lot ID: Customer Purchase Order # PO Internal Fox Sales Order # Dates that the XpressO part was shipped from the factory : 1000 on 10/18/2007, 1000 on 10/21/2007 The assigned customer part#: The Model specification: FXO-LC Serial Number: 218 Configuration Machine: Manufacturing Center # 4 Raw material used : PXO12-4-HC7-24-D Silicon foundry manufacturing lot: Z75002 Date and Time of configuration: 10/5/ :05 Optimization Code : M=0 Static electrical test of the actual part: 200 MHz, PPM OFFSET=3 PPM, ICC=90 mA Operator ID# :#318

9 A


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