Download presentation

Published byElaine Vergin Modified over 3 years ago

1
**Morgan Kaufmann Publishers Arithmetic for Computers**

April 1, 2017 CprE 381 Computer Organization and Assembly Level Programming, Fall 2013 Chapter 3 Arithmetic for Computers Zhao Zhang Iowa State University Revised from original slides provided by MKP Chapter 1 — Computer Abstractions and Technology

2
**The University of Adelaide, School of Computer Science**

1 April 2017 Announcements Midterm Exam 1 on Friday Oct. 3, 9:00-9:50am 12.5% weight of the overall grade No quizzes homework this week Midterm review 1 on Wednesday §2.8 Supporting Procedures in Computer Hardware Chapter 2 — Instructions: Language of the Computer — 2 Chapter 2 — Instructions: Language of the Computer

3
**Review of Week 5 Bubble sort code FP instructions**

FP pat of the call convention ARM and x86 ISAs Chapter 1 — Computer Abstractions and Technology — 3

4
**Exam 1 Open book, open notes, calculator are allowed**

E-book reader is allowed Must be put in airplane mode Coverage Chapter 1, Computer Abstraction and Technology Chapter 2, Instructions: Language of the Computer Some contents from Appendix B MIPS floating-point instructions Chapter 1 — Computer Abstractions and Technology — 4

5
**Exam Question Types Short conceptual questions**

Calculation: speedup, power saving, CPI, etc. MIPS assembly programming Translate C statements to MIPS (arithmetic, load/store, branch and jump, others) Translate C functions to MIPS (call convention) Among others Suggestions: Review slides and textbook Review homework and quizzes Redo homework questions Chapter 1 — Computer Abstractions and Technology — 5

6
**Arithmetic for Computers**

Morgan Kaufmann Publishers 1 April, 2017 Arithmetic for Computers §3.1 Introduction Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation and operations Chapter 3 — Arithmetic for Computers — 6 Chapter 3 — Arithmetic for Computers

7
**Integer Addition 1-bit adder Inputs: A, B, C (carry input)**

Output Sum, Cout (carry output) Try drawing the truth table Performance: 3 gate delays 3 gate delays on Sum (three layers of gates) 2 gate delays on Cout Chapter 1 — Computer Abstractions and Technology — 7

8
**Morgan Kaufmann Publishers**

1 April, 2017 Integer Addition N-bit Adder example: 7 + 6 This is called ripple-carry adder 32-bit adder has 31×2+3 = 65 gate delays 31×2 for carry ripping, plus 3 for the last Sum Faster design: Carry look-ahead adder (CLA) §3.2 Addition and Subtraction Chapter 3 — Arithmetic for Computers — 8 Chapter 3 — Arithmetic for Computers

9
**Addition Overflow Overflow if result out of range**

Adding +ve and –ve operands, no overflow Adding two +ve operands Overflow if result sign is 1 Adding two –ve operands Overflow if result sign is 0 Chapter 1 — Computer Abstractions and Technology — 9

10
**Morgan Kaufmann Publishers**

1 April, 2017 Integer Subtraction Add negation of second operand Example: 7 – 6 = 7 + (–6) +7: … (+6: … ) –6: … : … An adder can do subtraction, with simple circuit extension Invert every bit of the 2nd operand Set the carry input bit to be 1 Chapter 3 — Arithmetic for Computers — 10 Chapter 3 — Arithmetic for Computers

11
**Overflow in Subtraction**

Overflow if result out of range Subtracting two +ve or two –ve operands, no overflow Subtracting +ve from –ve operand Overflow if result sign is 0 Subtracting –ve from +ve operand Overflow if result sign is 1 Chapter 1 — Computer Abstractions and Technology — 11

12
**Morgan Kaufmann Publishers**

1 April, 2017 Dealing with Overflow Some languages (e.g., C) ignore overflow Use MIPS addu, addui, subu instructions Other languages (e.g., Ada, Fortran) require raising an exception Use MIPS add, addi, sub instructions On overflow, invoke exception handler Save PC in exception program counter (EPC) register Jump to predefined handler address mfc0 (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action Chapter 3 — Arithmetic for Computers — 12 Chapter 3 — Arithmetic for Computers

13
**Arithmetic for Multimedia**

Morgan Kaufmann Publishers 1 April, 2017 Arithmetic for Multimedia Graphics and media processing operates on vectors of 8-bit and 16-bit data Use 64-bit adder, with partitioned carry chain Operate on 8×8-bit, 4×16-bit, or 2×32-bit vectors SIMD (single-instruction, multiple-data) Saturating operations On overflow, result is largest representable value Example: = 255 for 8-bit addition c.f. 2s-complement modulo arithmetic E.g., clipping in audio, saturation in video Chapter 3 — Arithmetic for Computers — 13 Chapter 3 — Arithmetic for Computers

14
**Morgan Kaufmann Publishers**

1 April, 2017 Multiplication §3.3 Multiplication Start with long-multiplication approach multiplicand 1000 × multiplier product Length of product is the sum of operand lengths Chapter 3 — Arithmetic for Computers — 14 Chapter 3 — Arithmetic for Computers

15
**Control-Test Unit Design**

Morgan Kaufmann Publishers 1 April, 2017 Control-Test Unit Design A state machine of N states Each state represents a step State 0 => 1 => 2 => … => N-1 Input m(0): Bit 0 of multiplier Outputs Shift-right control to the multiplier Shift-left control to the multiplicand ALU operation type (select addition) Product register write-enable: Enable if m(0) = ‘1’, disable if m(0) = ‘0” Chapter 3 — Arithmetic for Computers — 15 Chapter 3 — Arithmetic for Computers

16
**Morgan Kaufmann Publishers**

1 April, 2017 Optimized Multiplier Perform steps in parallel: add/shift Utilized the unused bits in product to save multiplier Same performance: N additions per multiplication Chapter 3 — Arithmetic for Computers — 16 Chapter 3 — Arithmetic for Computers

17
**Morgan Kaufmann Publishers**

1 April, 2017 Faster Multiplier Uses multiple adders Cost/performance tradeoff Use 32-bit adders instead of 64-bit ones Can be pipelined: Several multiplication performed in parallel Chapter 3 — Arithmetic for Computers — 17 Chapter 3 — Arithmetic for Computers

18
**Morgan Kaufmann Publishers**

1 April, 2017 MIPS Multiplication Two 32-bit registers for product HI: most-significant 32 bits LO: least-significant 32-bits Instructions mult rs, rt / multu rs, rt 64-bit product in HI/LO mfhi rd / mflo rd Move from HI/LO to rd Can test HI value to see if product overflows 32 bits mul rd, rs, rt Least-significant 32 bits of product –> rd Chapter 3 — Arithmetic for Computers — 18 Chapter 3 — Arithmetic for Computers

Similar presentations

OK

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department.

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department.

© 2018 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on software company profiles Ppt on google self driving car Person focused pay ppt online Download ppt on time management for students Ppt on earthen dam construction Ppt on section 188 of companies act 2013 Ppt on kotak life insurance Ppt on team building in hindi Ppt on carburetor system diagram Ppt on poverty and unemployment in india