1. Lec 13Systems Architecture1 Systems Architecture Lecture 13: Integer Multiplication and Division Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).

2. Lec 13Systems Architecture2 Introduction Objective: To provide hardware support for MIPS integer multiplication and divide instructions. To understand how to implement multiplication and division in hardware. Topics –Review MIPS ALU design –Review integer multiplication and division –MIPS integer multiply and divide instructions –Multiplication algorithms –Division algorithms –Multiply/Divide unit

3. Lec 13Systems Architecture3 Support for SLT and Overflow Detection

4. Lec 13Systems Architecture4 MIPS ALU

5. Lec 13Systems Architecture5 MIPS Integer Multiply and Divide Hi and Lo registers –mfhi –mflo Signed and unsigned multiply –mult –multu Divide instructions –div –divu –quotient is available in Lo and remainder in Hi

6. Lec 13Systems Architecture More complicated than addition –accomplished via shifting and addition More time and more microchip area We will look at 3 versions based on a simple algorithm we learned in elementary school: 0010 (multiplicand) __x_1011 (multiplier) Negative numbers: convert and multiply –there are better techniques, we won’t look at them Multiplication in Hardware

7. Lec 13Systems Architecture Multiplication Hardware – Algorithm 1 Datapath Control

8. Lec 13Systems Architecture8 http://www.cs.rpi.edu/~hollingd/comporg.2000/Notes/Mult.PDF

9. Lec 13Systems Architecture9 Multiplication Hardware – Algorithm 2 Datapath Control

10. Lec 13Systems Architecture Multiplication Hardware – Algorithm 3 Note: Multiplier starts in right half of product. Datapath Control

11. Lec 13Systems Architecture11 http://www.cs.rpi.edu/~hollingd/comporg.2000/Notes/Mult.PDF

12. Lec 13Systems Architecture Fast Multiplication Hardware Unroll the addition “loop” Use 32 32-bit adders Each adder produces 32-bits and a carry-out The least significant bit of each intermediate sum is a bit of the product. The other 31 bits and the carry-out are passed along to the next adder.

13. 12 October 2015Chapter 3 — Arithmetic for Computers 13 Faster Multiplier Uses multiple adders –Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel

14. Lec 13Systems Architecture14 Division Hardware – Algorithm 1

15. Lec 13Systems Architecture15 Division Hardware – Algorithm 3

16. Lec 13Systems Architecture16 http://www.cs.rpi.edu/~hollingd/comporg.2000/Notes/Mult.PDF