Download presentation

1
A Simple ALU Binary Logic

2
**Outline Binary Logic Representation of Logic Gates**

Constructing a 1-bit adder Constructing an n-bit adder

3
**Binary Logic A computer works using digital electronics.**

There are only High and Low voltages All computer logic is based on the manipulation of these Abstractly, High is interpreted as 1 (true) Low is interpreted as 0 (false)

4
Logic Circuit A logic circuit takes in a number of input lines (A, B, C, ...) and has a number of output lines (X,Y,Z,...) A X B Y C Z

5
**Logic Basics Every expression evaluates to 1 or 0 NOT OR AND**

~A (“A bar”) is the complement of A, i.e. 1-A OR A + B is 1 if and only if at least one of A or B is 1, else 0 AND A.B is 1 if and only if both A and B are 1, else 0

6
**Truth Tables A B A+B A.B A ~A 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1**

A ~A 0 1 1 0 A B C A.B A.C B+C A.(B+C) A.B+A.C A.(B+C)=A.B+A.C

7
Gates A A.B AND Gate B A OR Gate A+B B ~A Inverter (NOT) A

8
**Representations of Integers**

Positive integers are represented by strings of binary digits - of fixed length given by the word length (eg, 32 bits). Numbers in the range 0 to can be represented. 1 31 LSB MSB

9
Negative Numbers We have to have a way to represent negative numbers and 0. If the word length is n, then there are 2n bit-patterns possible - there cannot be an equal number of positive and negative numbers represented. Suppose n=3, and consider the following: 000two = 0ten 100two = -4ten 001two = 1ten 101two = -3ten 010two = 2ten 110two = -2ten 011two = 3ten 111two = -1ten

10
Two’s Complement For an n-bit word, the MSB is called the ‘sign bit’, which if 1 determines a negative number. An n-bit word: (bn-1bn-2...b1b0)two represents the decimal number: Eg, if n=4, 1101 = = -3. Eg, if n=5, = = -10

11
**Negating a Number A simple technique for negating a number: Convert:-**

Invert each bit, and then add 1. Convert:- 10110 = = 2ten+8ten = 10ten 1101 = 0011 = 1ten + 2ten = 3ten 0011 = 1101 = -8ten+4ten+1ten = -3ten

12
Arithmetic Binary arithmetic, addition and subtraction are similar to decimal: work from least significant bit to most significant bit using carries where necessary. A fundamental issue on a computer is the fixed word size The operands and result is dependent on the word length, and sometimes the result will be too small (negative) or too large (positive) to be represented.

13
**Addition and Subtraction**

Examples, n=4 (OVERFLOW) ten ten 1101 = = -3ten Subtraction = (two’s complement) = 0001 = 1ten

14
Overflow (Patterson) Decimal Binary Decimal 2’s Complement 0000 0000 1 0001 -1 1111 2 0010 -2 1110 3 0011 -3 1101 4 0100 -4 1100 5 0101 -5 1011 6 0110 -6 1010 7 0111 -7 1001 -8 1000 Examples: = but = but ... 1 1 1 1 1 1 1 7 1 1 - 4 3 - 5 + 1 1 + 1 1 1 1 1 - 6 1 1 1 7

15
**Overflow Detection (Patterson)**

Overflow: the result is too large (or too small) to represent properly Example: - 8 < = 4-bit binary number <= 7 When adding operands with different signs, overflow cannot occur! Overflow occurs when adding: 2 positive numbers and the sum is negative 2 negative numbers and the sum is positive 1 1 1 1 1 1 1 7 1 1 - 4 3 - 5 + 1 1 + 1 1 1 1 1 -6 1 1 1 7

16
Designing a 1-bit Adder A 1-bit adder must follow the following rules:- a b R C a, b inputs, R result, C carry.

17
**Logic Circuit for 1-bit Adder**

Notice that R = (~a).b + a.(~b) C = a.b a b r c

18
n-bit Adder Problem with previous circuit is that there is no way to combine a sequence of adders together the carry of one addition must be passed to the next. Need a structure as: carryin a b r carryout

19
**Truth Table Logic diagrams can be constructed for each of carryout**

and Result, using the results below. Cout = a.(~b).c + a.b.(~c) + (~a).b.c + a.b.c = a.c+b.c+a.b Result = (~a).(~b).c + (~a).b.(~c) + a.(~b).(~c) + a.b.c

20
**Logic Diagrams for CarryOut and Sum (Patterson)**

CarryOut = B & CarryIn | A & CarryIn | A & B Result = A XOR B XOR CarryIn CarryIn A B CarryOut CarryIn A Result B

21
**Link 1-bit adders for n-bit**

carryin a b r0 carryout/carry in A chain of 1-bit adders is formed where the carryout of each becomes the carryin of the next. The result is the sequence of results from LSB to MSB. a r1 b carryout

22
**(Patterson) Notice how the 1-bit adders are cascaded together.**

CarryIn0 A0 1-bit ALU Result0 B0 A1 B1 1-bit ALU Result1 CarryIn1 CarryOut1 CarryOut0 Notice how the 1-bit adders are cascaded together. A2 B2 1-bit ALU Result2 CarryIn2 CarryOut2 CarryIn3 A3 1-bit ALU Result3 B3 CarryOut3

23
**Summary Binary logic Number representations Binary arithmetic**

two’s complement Binary arithmetic Constructing a 1-bit adder Constructing an n-bit adder ...next time --- floating point.

Similar presentations

Presentation is loading. Please wait....

OK

ECEN 248 Lab 4: Multiplexer Based Arithmetic Logic Unit

ECEN 248 Lab 4: Multiplexer Based Arithmetic Logic Unit

© 2018 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google