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Layout in Deep Submicron...or, what are all these rules? Ron Ho 9/21/00.

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Presentation on theme: "Layout in Deep Submicron...or, what are all these rules? Ron Ho 9/21/00."— Presentation transcript:

1 Layout in Deep Submicron...or, what are all these rules? Ron Ho 9/21/00

2 Introduction Weve learned all of the standard DRs –EE271, taping out 0.8 to 0.25 m chips There are also a number of newer DRs –For more advanced processes, fab steps –They may affect you in future tapeouts A brief intro to some of these rules –Not sure what processes use these...

3 Outline New metal density rules Antenna rules and proper application Phase-shift region coloring Optical proximity correction Odds and ends

4 resist Metal Density Old rule: minimum metal density –For Al, metals were etched away ILD metal High densityLow density This etching step takes a lot longer (microloading) Solution: Add dummy metal structures here to maintain minimum metal density

5 Metal Density New rule: max/min metal density –For Cu, metals are poured (damascene) –Review of dual-damascene An amateurs view of dual damascene (via-first variation) Ta barrier layer to prevent Cu from diffusing into Si SiN layer for etch stop M2 M1

6 Metal Density –Min rule: Ta barrier is hard to remove –Max rule: Cu metal is much softer than Ta Selectivity of Cu is 20x higher than for Ta Low density: Mandate min. metal density Barrier tough to remove High density: Mandate max. density and width Softness of Cu results in dishing

7 Metal Density Min density: Around 30%/layer, in stepped windows Windows are around 1mmx1mm square, steps of ~100 m Dummification metal structures required to add metal Max density Around 70%/layer, again in stepped windows Usually, max width + min spacing -> 90% density Insert slots in lines or turn wide wires into parallel lines Rules checked in Dracula (not Magic)

8 Reactive ion etch charges up metal lines –Charge can accumulate and zap a gate oxide –If a gate sees a long metal before a diffusion does Antenna Rules m4 m3 m2 m1 gate 100 Safe: m3 is too short to accumulate very much charge; wont kill gate gate 2000 Dangerous: lots of m3; will probably accumulate lots of charge and then blow oxide diff

9 Antenna Rules Two solutions: bridging and node diodes –Bridging attaches a higher layer intermediary –Diode is a piece of diffusion to leak away charge m4 m3 m2 m1 psub gate 2000 Bridging keeps gate away from long metals until they drain through the diffusion gatendiff Node diodes are inactive during chip operation (reverse-biased p/n); let charge leak away harmlessly

10 Antenna Rules Bridge or add node diodes if area ratio > limit –Most rulesets today use Sum(metal_area_not_tied_to_diff)/gate_area –Examples from previous slides Be careful to account for etch rate! –Etching rates vary depending on geometries –May expose antennas of smaller or larger size –Note: this applies to Al, not Cu damascene

11 Antenna Rules In areas of lower metal density (microloading) –Slower etch can imply longer-lasting islands Large island of metal lasts for a short time, but can be enough to gather a fatal charge, especially if node X were already close to the ratio limit Node x

12 Antenna Rules In regions of lots of narrowly space wires –Can get a slower etch effect from e - shading –Especially if resist aspect ratio is high Etching particles dont enter trench as easily Differential in etch rates, creating islands of metal abcd Node c, e.g., has an etch-antenna that includes a, b, and d

13 Antenna Rules Antenna rules work incrementally –Disconnect all above M1; check non-diff nodes –Add M2; check non-diffusion-protected nodes; etc. Stefanos has such a flow for Magic (ext2ant) Ideally, antenna rules would include etching –Calculate ratios based on neighbors and etchrates –In practice, use a fudge factor on the allowed ratio Cu relaxes antenna rule (lower ratio) –Still must etch ILD, but no etchrate variability

14 Phase-Shifting Masks Lithography uses (partially) coherent light –Wavelength today is 248nm; changes slowly Kahng et. al., 1999 DAC

15 Phase-Shifting Masks PSM enables higher resolution patterning –Exploiting constructive/destructive light Kahng et. al., 1999 DAC

16 Phase-Shifting Masks PSM done typically on poly and contact –Most critical layers for narrow lines; PSM $$$ Around any line, we need to flip phases This is a 2-coloring problem 0o0o 0o0o 0o0o 180 o 0o0o 0o0o 0o0o Phase conflict here will create an unwanted line; need trim mask to kill it

17 Phase-Shifting Masks Two principal design rule effects –Orthogonal gates cannot be too close –Avoid interdigitating poly These should be checkable directly in Magic 0o0o 180 o Orthogonal gates need to have increased spacing to allow room for the 0 o section to the right of the vertical gate Trying to duck the poly-poly rule by interdigitating the fingers is bad

18 Optical Proximity Correction Also known as serifs and dog-ears –Layout is not WYSIWYG anymore Patterning through a reticle is tough –Holes in reticle act as low-pass filter Blurred edges Squares in mask are blobby ovals in production –We can predistort the image to compensate Analogous to channel equalization

19 Optical Proximity Correction Standard fixes include: –Outside corner dog-ears –Inside corner cut-outs –Long line embellishments

20 Optical Proximity Correction Example Schellenberg et. al., 1999 SPIE

21 Optical Proximity Correction This is a back-end flow, done after tape-out –Designers are unaware of OPC for the most part –Only real restriction: limit use of 45 o routing 45 o routes, with OPC, need more spacing to other wires Only important to those of us who use Cadence tools... –OPC does explode the database size Imagine the size of a microprocessor database...

22 Odds and Ends Via spacing rules will change –Center-to-center instead of edge-to-edge Reflect the fact that vias are really more circular –Most efficient packing is not a rectangular array More like a checkerboard pattern –Checkable in Magic (shrink, then edge-edge)

23 Odds and Ends EM rules are relaxed with Cu metal –Vias in Cu processes are also Cu (poured) Expect that via EM rules are also relaxed –However, vias have some EM problems Void formation at vias –Defects in the hole formed during the dielectric etch Void formation along the Cu wire –Adhesion of the Cu to the barrier metal above isnt great –Voids will travel down the wire and get stuck in the vias

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