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Chap9. BIST 1 Built-In Self-Test. Chap9. BIST 2 Built-in Self Test (BIST) Basics Test Pattern Generators Response Analyzers BIST Examples BIST of PLAs.

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Presentation on theme: "Chap9. BIST 1 Built-In Self-Test. Chap9. BIST 2 Built-in Self Test (BIST) Basics Test Pattern Generators Response Analyzers BIST Examples BIST of PLAs."— Presentation transcript:

1 Chap9. BIST 1 Built-In Self-Test

2 Chap9. BIST 2 Built-in Self Test (BIST) Basics Test Pattern Generators Response Analyzers BIST Examples BIST of PLAs BIST

3 Chap9. BIST 3 BIST - General Organization Test Generator Circuit Under Test (CUT) Response Compressor BIST Basics

4 Chap9. BIST 4 BIST - Goal Reduce input/output pin signal traffic. Permit easy circuit initialization and observation. Eliminate as much test pattern generation as possible. Achieve fair fault coverages on general class of failure mode. Reduce test time. Execute at-speed testing. Test circuit during burn-in. BIST Basics

5 Chap9. BIST 5 BIST Issues Area overhead Performance degradation Fault coverage Ease of Implementation Capability for system test Diagnosis capability BIST Basics

6 Chap9. BIST 6 BIST Techniques Stored Vector Based –Microinstruction support –Stored in ROM Algorithmic Hardware Test Pattern Generators –Counter –Linear Feedback Shift Register –Cellura Automata BIST Basics - LFSR

7 Chap9. BIST 7 Linear Feedback Shift Register D1D1 D2D2 D3D3 D4D4 + Type 1 D1D1 D2D2 D4D4 + Type 2 Unit delay - D Flip flop Modulo 2 adder - XOR gate Modulo 2 multiplier -connection BIST Basics - LFSR D3D3

8 Chap9. BIST 8 LFSR - Why? Simple and Regular Structure Compatible with scan DFT design Capable of exhaustive and/or pseudo exhaustive testing Low aliasing probability BIST Basics - LFSR

9 Chap9. BIST 9 LFSR - Recurrence Relation Generating Function Characteristic polynomial gxgx i i i n () 0... DnDn D n-1 D2D2 D3D3 D1D1 g n-1 + g2g2 + g1g I s a -1 a -2 a a -n+1 a -n C s a m-1 a m-2 a m-3... a m-n+1 a m-n BIST Basics - LFSR

10 Chap9. BIST 10 LFSR - Recurrence Relation (continue) G(x)G(x) BIST Basics - LFSR m=0m=0 = a m x m = g i a m-i x m = g i x i a m-i x m-i = g i x i [ a -i x -i a -1 x -1 + a m x m ] = g i x i [ a -i x -i a -1 x -1 + G(x) ] m=0m=0 i =1 n n m=0m=0 i =1 n m=0m=0 i =1 n a m = g i a m-i i =1 n

11 Chap9. BIST 11 LFSR - Recurrence Relation (continue) BIST Basics - LFSR G(x) is function of initial state and g(x)

12 Chap9. BIST 12 LFSR Example D4D4 D3D3 D2D2 D1D BIST Basics - LFSR +

13 Chap9. BIST 13 LFSR - Definitions If the sequence generated by an n-stage LFSR has period 2 n -1, then it is called a maximum-length sequence. The characteristic polynomial associated with maximum-length sequence is called a primitive polynomial. An irreducible polynomial is one that cannot be factored; i.e., it is not divisible by any other polynomial other than 1 and itself. BIST Basics - LFSR

14 Chap9. BIST 14 LFSR - Theories If the initial state of an LFSR is a -1 =a -2 =...= a 1-n =0, a -n =1, then the LFSR sequence {a m } is periodic with a period that is the smallest integer k for which P(x) divides (1+x k ) An irreducible polynomial P(x) satisfies the following two conditions is a primitive polynomial: –It has an odd number of terms including the 1 term. –If its degree n is greater than 3, then P(x) must divide 1+x k, where k=2 n -1 BIST Basics - LFSR

15 Chap9. BIST 15 LFSR - Properties The number of 1s in an m-sequence differs from the number of 0s by one. An m-sequence produces an equal number of runs of 1s and 0s. In every m-sequence, one half the runs have length 1, one fourth have length 2, one eighth have length 3, and so forth, as long as the fractions result in integral numbers of runs. BIST Basics - LFSR

16 Chap9. BIST 16 LFSR - Properties (continue) M-sequences generated by LFSRs are called pseudo random sequence. The autocorrelation of any output bit is very close to zero. The correlation of any two output bits is very close to zero. BIST Basics - LFSR

17 Chap9. BIST 17 LFSR - Polynomial Multiplication D1D1 + g1g1 D2D2 + g n-2 D n-1 + g n-1 DnDn + gngn g0g0... input f(x) output h(x) BIST Basics - LFSR

18 Chap9. BIST 18 LFSR - Polynomial Multiplication D1D1 D2D2 D3D3 + D4D4 + Output stream D 4 D 3 D 2 D 1 Input stream x 7 x 5 x 4 x 2 1 BIST Basics - LFSR

19 Chap9. BIST 19 LFSR - Polynomial Division D1D1 + g1g1 + g n-2 + g n-1 gngn g0g0... inputoutput + D2D2 D n-1 DnDn BIST Basics - LFSR

20 Chap9. BIST 20 LFSR - Polynomial Division (example) Input Output M(x) Q(x) D1D1 D2D2 D3D3 + D4D4 + M(x) D 3 D 2 D 1 D 0 Q(x) after 4 shifts BIST Basics - LFSR x+x 2 +x 4 +x 5 +x 7 +x 8 1+x+x 4 1 +x 2 +x 3 (x 8 +x 7 +x 5 +x 4 +x 2 +x) (x 4 +x 3 +1) = x 4 +x+1 R(x) = x 3 +x 2 +1

21 Chap9. BIST 21 LFSR - Summary LFSRs have two types. LFSRs can implement polynomial division and multiplication in GF(2). As polynomial multipliers, LFSRs are capable of generating random vector. As polynomial divisors, LFSRs are capable of compressing test responses. BIST Basics - LFSR

22 Chap9. BIST 22 Cellura Automata (CA) A One-Dimensional Array of Cells. Each cell contains a storage device and next state logic. Next state is a function of current state of the cell and its neighboring cells. Three-Cell Neighbor -- von Newmann Neighborhood DQDQ Next State DQDQ DQDQ Next State Next State BIST Basics - CA

23 Chap9. BIST 23 Cellura Automata - Name Name of CA Functions is determined by its truth table. BIST Basics - CA State A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 C i+1 C i C i-1 Next State KMap F CA A0A0 A2A2 A1A1 A3A3 A5A5 A4A4 A6A6 A7A7 Example:Name = = (defined by Wolfram) 0101 C i C i C i

24 Chap9. BIST 24 Cellura Automata - Hardware BIST Basics - CA DQDQ Fca DQDQ DQDQ DQDQ DQDQ DQDQ 0 0 CA with Null Boundary Condition Standard - All the CAs are of the same type Hybrid - The CAs are of different type

25 Chap9. BIST 25 Cellura Automata - Hardware BIST Basics - CA DQDQ Fca DQDQ DQDQ DQDQ DQDQ DQDQ CA with cyclic Boundary Condition

26 Chap9. BIST 26 BIST - Pattern Generation PG Hardware Stored Patterns Counter Based LFSR Based Cellura Automata Pattern Generated Deterministic Pseudorandom Exhaustive Pseudo exhaustive BIST - TestGen

27 Chap9. BIST 27 TG - Stored Pattern Functional Chip Tests Test for structured logic such as ILA Supplemental test for uncovered faults Test control for other methods Architecture support self test command BIST - TestGen - Stored Pattern

28 Chap9. BIST 28 Stored Pattern- Supplement for Uncovered faults Hard-to-detect faults not covered by random testing BIST - TestGen - Stored Pattern hard to detect fault

29 Chap9. BIST 29 TG - Counter Based Generates regular test sequences such as walking sequences and counting sequences for memory and interconnect testing Walking Sequence Counting Sequence BIST - TestGen - Counter Based

30 Chap9. BIST 30 TG - LFSR Exhaustive Testing Pseudoexhaustive Testing Pseudorandom Testing Weighted Pseudorandom Testing BIST - TestGen - LFSR

31 Chap9. BIST 31 TG - Exhaustive Testing Apply all possible input combinations A complete functional testing 100% coverage on all possible faults Testing time and hardware overhead are the major considerations for circuits with large number of inputs. BIST - TestGen - LFSR LFSR CUT SA

32 Chap9. BIST 32 BIST - Pseudo-exhaustive Testing (PET) Apply all possible input combination to every partitioned subcircuits. 100% faults coverage on single faults and multiple faults within the subcircuit. Testing time is determined by the number of subcircuits and the number of inputs to the subcircuit. Partitioning is a difficult task.

33 Chap9. BIST 33 TG - PET Hardware Example Subcircuit under test MUX LFSRLFSR SASA CUT normal inputs BIST - TestGen - LFSR

34 Chap9. BIST 34 BIST - Pseudo Random Testing Apply random test sequence generated by LFSR/CA. Simplest to design and implement Lowest in hardware overhead Fault coverage is a function of the test length and the testability of the circuits BIST - TestGen - LFSR

35 Chap9. BIST 35 BIST - Pseudo Random Testing Hardware CombinationalSequential LFSR Combinational circuit SA LFSR Combinational circuit SA (Circular BIST) BIST - TestGen - LFSR (BEST)

36 Chap9. BIST 36 BIST - Pseudo Random Testing Hardware Circuit Under Test Shift registerLFSR SA LFSR SA SRSR SRSR SRSR CUT BIST - TestGen - LFSR (CEBT)(STUMPS)

37 Chap9. BIST 37 Pseudo Random Test Length e th :Escape Threshold g min :the detection probability of the hardest to detect fault by a random vector k:the number of faults with detection probability 2g min Example 1: e th =0.001, g min =1E-5, k=5 m=851,716 Example 2: e th =0.001, g min =1E-5, k=50 m=1,081,973 BIST - TestGen - LFSR

38 Chap9. BIST 38 BIST - Weighted Pseudo Random Test LFSR 1/83/41/27/81/2 BIST - TestGen - LFSR DQDQ 123 DQDQ 193 DQDQ 61 DQDQ 114 DQDQ 228 DQDQ 92 DQDQ 25 0 LFSR BasedWeighted Celluar Automaton

39 Chap9. BIST 39 BIST - Response Compression Introduction Ones-Count Compression Transition-Count Compression Syndrome-Count Compression Signature Analysis Space Compression BIST - ResComp

40 Chap9. BIST 40 BIST - Response Compression Bit-to-bit Comparison is infeasible for BIST. Compress a very long output sequence into a single signature. Compare the compressed word with the prestored gold signature to determine the correctness of the circuit. Many output sequences may have the same signature after the compression, the aliasing problem. Poor diagnosis resolution after compression. BIST - ResComp

41 Chap9. BIST 41 Ones-Count - Hardware Apply predetermined patterns Count the number of ones in the output sequence. Test Pattern CUT Counter Clock BIST - ResComp

42 Chap9. BIST 42 Ones Counter - Aliasing Aliasing Probability m:the test length r:the number of ones r=m/2, the case with the highest aliasing probability r=m and r=0, no aliasing probability For combinational circuits, the input sequence can be permuted without changing the count. BIST - ResComp

43 Chap9. BIST 43 Transition Count Apply predetermined patterns Count the number of the transitions (0 1 and 1 0) Test Pattern CUT Counter Clock DFF BIST - ResComp

44 Chap9. BIST 44 Transition Count Aliasing Probability m:the test length r:the number of transitions r=m/2, highest aliasing probability. r=0 and r=m, no aliasing probability For combinational circuits, the input sequence cannot be permuted. One can reorder the test sequence to minimize the aliasing probability. BIST - ResComp

45 Chap9. BIST 45 Syndrome Testing Apply random patterns. Count the probability of 1. The property is similar to that of ones count. random test pattern CUT Syndrome counter Counter / Clock Syndrome BIST - ResComp

46 Chap9. BIST 46 Signature Analysis Apply predetermined test patterns. Divide the Output Sequence by LFSR. Test Pattern CUT LFSR BIST - ResComp

47 Chap9. BIST 47 Signature Analysis Aliasing Probability m:test length, n:length of LFSR Aliasing probability is output independent. An LFSR with two or more nonzero coefficient detect any single faults. An LFSR with primitive polynomial detect any double faults separated less than 2 n -1 An LFSR with g 0 =1 detects all burst error of length less than n. BIST - ResComp

48 Chap9. BIST 48 Multiple Input Signature Register (MISR) D4D4 + D3D3 + D2D2 + D1D1 + type 2type 1 D4D4 + D3D3 + D2D2 + D1D1 + + BIST - ResComp

49 Chap9. BIST 49 Space Compression Use space compression to handle large output circuits. Use XOR gates to compress space. Use Error Control Coding to achieve better fault coverage. Example: A 16 SEC-DED code compresses 16 outputs into 5. BIST - ResComp

50 Chap9. BIST 50 BIST - Space and Time Compression CUT TC SC CUT TC SC Space-Time CompressionTime-Space Compression BIST - ResComp

51 Chap9. BIST 51 BIST Examples HP Focus Chip, Functional Chip Test Built-in Logic Block Observation (BILBO) [Koenemann 79] Centralized and Separate Board Level BIST (CSBL) [Benowitz 75] Built-in Evaluation and Self-Test (BEST) [Resnick 83] Random-Test Socket (RTS) [Bardell 82] LSSD On-Chip Self Test (LOCST) [LeBlanc 84] Self test using MISR and Parallel SRSG (STUMPS) [Bardell 82] BIST - Example

52 Chap9. BIST 52 BIST Examples (cont.) Concurrent BIST Architecture (CBIST) [Saluja 88] Centralized and Embedded BIST with Boundary Scan (CEBS) Random Test Data (RTD) [Bardell 87] Simultaneous Self Test (SST) [Gupta 82] Cyclic Analysis Testing System (CATS) [Burkness 87] Circular Self-Test Path (CSTP) [Krasniewski 89] BIST - ResComp

53 Chap9. BIST 53 BIST - HP Focus Chip (Stored Pattern) Chip Summaries –450,000 NMOS devices, 300,000 Nodes –24MHz Clocks, 300K bits of on-chip ROM – Used in HP computer BIST Microprogram –Use microinstructions dedicated for testing –100K-bit BIST microprogram in CPU ROM –Executes 20 million clock cycles –Greater than 95% stuck-at coverage –A power-up test used in system test, filed test, and wafer test BIST - Example

54 Chap9. BIST 54 BIST - BILBO Built-in Logic Block Observation [Koenemann 79.80] 0 1 MUX Z1Z1 QD Q Q1Q1 Z2Z2 D Q Q Q2Q2... QD Q Q n-1 ZnZn D Q Q QnQn S0S0... SiSi B2B2 B1B1 C1C1 BILBO1 BILBO2 C2C2 BILBO3 C3C3 B 1 B 2 BILBO 0 0shift register 0 1reset 1 0MISR (input constant LFSR) 1 1parallel load (normal operation) BIST - Example

55 Chap9. BIST 55 BIST - CSBL Centralized and Separate Board-Level BIST [Benowitz 75] Use only one Signature Register Tests repeat m times to reduce hardware cost CUT (C or S) MUX SISRCounter PRPG n k 1 m n m 1 PIs POs BIST - Example

56 Chap9. BIST 56 BIST - BEST Built - Evaluation and Self Test [Resnick 83] Pseudo random testing Hardware overhead is low Test length can be long for CUT with random-pattern resistant faults. PRPG CUT (C or S) MISR PIPO BIST - Example

57 Chap9. BIST 57 Random-Test socket [Bar dell 82] Combine LSSD Scan Chain and BIST Can insert test points to reduce test length for random- pattern resistant faults BIST - RTS CUT (S) S in S out ClocksControls PRPG MISR SRSG R1R1 R3R3 R2R2 SISR R4R4 BIST controller BIST - Example

58 Chap9. BIST 58 BIST - LOCST LSSD On-Chip Self-Test [LeBlanc 84] Boundary scan is required to unify the test architecture Single scan chain may cause high test time overhead. CUT (S) SiSi S0S0 SRSG PIs SRL R1R1 SISR POs SRL R2R2 On-chip monitor (OCM) Error-detection circuitry S in Error signal Control signals BIST - Example

59 Chap9. BIST 59 BIST - STUMPS Self-Test using MISR and Parallel SRSG [Bardell 82,84] Multiple scan chain to reduce test time... PIs... POs PRPG Scan path... CUT (S) SoSo So*So* External logic BIST - Example

60 Chap9. BIST 60 BIST - CBIST Concurrent Built-in Self Test [Saluja 88] Detect test patterns from normal inputs sequence Once a pattern is detected, compress the response and tick the test clock. If waited too long, insert a test pattern from PRPG. Comparator PRPG MUX N / T Normal inputs CUT (C) MISR Normal outputs EN CBIST Circuitry BIST - Example

61 Chap9. BIST 61 BIST - CEBS Centralized and Embedded BIST architecture with Boundary Scan [Komanytsky 82.83] A low cost version of RTS or LOCST CUT (S) SiSi SoSo Boundary-scan registerInput... Boundary-scan registerOutput PIs POs RPG (PRPG/SRSG) SR (MISR/SISR) S in S out BIST - Example

62 Chap9. BIST 62 BIST - RTD Random Test Data [Bazdell 87] Use MISR to replace internal storage devices for test generation and response comparison C MISR... PRPG... MISR S in S out PIsPOs R1R1 R3R3 R2R2 CUT... BIST - Example

63 Chap9. BIST 63 BIST - SST Simultaneous Self Test [Gupta 82] Similar to MISR but without LFSR part PO CUT Combinational PI BIST - Example

64 Chap9. BIST 64 BIST - CATS Cyclic Analysis Test System [Burkness 87] If more outputs than inputs, space compression is needed. If less outputs than inputs, an output drive multiple inputs. A synchronous feedback loops can be created, therefore may create races. BIST - Example x1x1 S x1x1 xnxn... z1z1 znzn S xnxn z1z1 znzn MUX... N / T Original Circuit BIST Circuit

65 Chap9. BIST 65 BIST - CSTP Circular Self Test Path [Krasniewski 89] Similar to SST except that boundaries are scanned Not all registers are self- test path registers. R1R1 R6R6 C1C1 C6C6 R5R5 C5C5 R7R7 R3R3 C3C3 R2R2 R4R4 C2C2 C4C4 R8R8 R R - conventional register - self-test path register POsPIs Key C... z1z1 z2z2 zmzm x1x1 x2x2 xmxm BIST - Example

66 Chap9. BIST 66 BIST - PLA General Structure BIST - PLA AND Plane First NOR Plane Input Decoders... PLA Inputs OR Plane Second NOR Plane Output Buffers... PLA Outputs. product lines.

67 Chap9. BIST 67 BIST - PLA Circuit Structure BIST - PLA x1x2x3z1z2 p1 p2 p3 Vdd Input Decoders Output Buffer Vdd

68 Chap9. BIST 68 BIST PLA - Fault Model Stuck-at faults (A) Bridging faults (B) Cross Point faults –Missing Device fault (C) –Extra Device faults (D) BIST - PLA A ANDOR B C D

69 Chap9. BIST 69 BIST PLA - Cross Point faults Growth - The missing device in AND plane causes an input variable to disappear from a product term. Shrink - The extra device in AND plane causes an input variable to appear in a implicant. Disappearance - The missing device in OR plane causes an implicant to disappear from a function. Appearance - The extra device in OR plane causes an implicant to appear in a function. BIST - PLA

70 Chap9. BIST 70 PLA Testing Test generation is difficult for large PLAs - Pseudorandom resistance due to large fan-ins Easily testable designs - Add moderate hardware overhead to make pattern generation easier - The general idea is to make each product line controllable and observable Built-In Self Test - A varieties of technique were proposed - The effectiveness is evaluated by Hardware overhead Test length Delay per test application

71 Chap9. BIST 71 The HJA Scheme Proposed by Hua, Jou and Abraham Solve pitch mismatch problem by using multiplexing in the Augmented Decoder Hardware Overhead: fair - AD, TPG, PC2 and PC3 Test length: good - 2M+P+2 Delay per test application: fair -Limited by the parity checkers

72 Chap9. BIST 72 The HJA Scheme (continue)

73 Chap9. BIST 73 TFA Scheme Proposed by Treuer, Fujiwara and Agarwal Hardware overhead: good - AD, PS, PC3 Test length: fair - 2MP + 2M + 1 Delay per test application: fair - Limited by the parity checker

74 Chap9. BIST 74 TFA Scheme (continue)

75 Chap9. BIST 75 HM Scheme Proposed by Hassan and McCluskey Hardware overhead: bad - A M-bit LFSR generates exhaustive patterns - Three LFSRs compress the results Test length: bad - Bad for PLAs with large number of inputs Delay per test application: good - Use signature analyzer instead of parity checkers

76 Chap9. BIST 76 HM Scheme (continue) L L AND Array G OR Array LS Inputs Output G: Maximum Length Sequence Generator L: Parallel LFSR LS: LFSR(s) Used to Compact the Outputs Complemented Bit Lines True Bit Lines

77 Chap9. BIST 77 DM Scheme Proposed by Daehn and Mucha Using nonlinear feedback shift registers for both pattern generation and response compression Hardware overhead: bad - Three slightly modified BILBOs Test length: good - 2M + P + Q + 1 Delay per test application: good

78 Chap9. BIST 78 DM Scheme (continue) BIST - PLA AND Plane BILBO1 Input Decoders OR Plane BILBO3 Input Decoders BILBO2

79 Chap9. BIST 79 The New BIST Design Hardware overhead: good - AD, PS and MISR Test length: fair - 2MP Delay per test application: good - No parity checkers

80 Chap9. BIST 80 The New BIST Design (continue)

81 Chap9. BIST 81 The New BIST Design Use AD and PS to evaluate each device in the AND array Use MISR with X Q + 1 as the characteristic polynomial - Hardware complexity is comparable to that of the parity checker Add one extra input - Make the product lines of the AND array all have an odd number of devices and an odd number of nondevices Add one or two product lines - Make the bit lines of the AND array all have an odd number of devices - Make the output lines all have an odd number of devices - Make the PLA have an odd number of product lines

82 Chap9. BIST 82 Fault Coverage MISR with X Q + 1 S i (x) = 1 + x + x 2 + x 4 = R i (x) = x + x 2 = S i+1 (x) = 1 + x 3 = In order to guarantee the detection of all modeled faults, the E(X) caused by some fault must satisfy the requirement of E(X) mod X Q + 1 0

83 Chap9. BIST 83 Fault Coverage Theorem 1: E(X) mod X Q if E(X) has an odd number of terms Theorem 2: All the single contact faults and stuck at faults cause E(X) to have an odd number of terms in the BIST design Theorem 3: R(X) mod X Q +1 has an odd number of terms if R(X) has an odd number of terms Corollary 1: F(X) mod X Q + 1 has an even number of terms if F(X) has an even number of terms Parity of fault-free signature is 1

84 Chap9. BIST 84 Fault Coverage Parity of faulty signature is 0 Short faults between two adjacent bit lines are detected by NOR gate E1 Short faults between two adjacent product lines are detected by the NOR gate E2 combined with a parity counter Short faults between two adjacent output are not 100% detectable

85 Chap9. BIST 85 Conclusion Deterministic test pattern generation is used to generate the efficient test patterns The simplest MISR is used to compress the results into only ONE bit The final signature can be further compressed into only ONE bit All the single stuck-at faults and contact faults are detected The design gives a better trade-off between the cost and the performance of BIST PLAs

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