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Built-In Self-Test

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**Built-in Self Test (BIST)**

Basics Test Pattern Generators Response Analyzers BIST Examples BIST of PLAs First. we will introduce the basics of BIST which include the. 1. Why do we need BIST, 2. The general aspect of BIST 3. The advantages and disadvantages of BIST. The following topics will be discussed in detail 1. Test pattern generation, counter, LFSR, cellura automata 2, Response analyzers such as ones count, syndrome count, transition count, signature analysis, and cellura automata. 3. BIST examples, some primitive and advanced BIST examples. 4. PLA - we look at PLA into detail. BIST

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**BIST - General Organization**

Test Generator Circuit Under Test (CUT) The basic structure of BIST include two extra modules. 1. Test pattern generator to generate desired test vectors. The possible generators include ROM, counters and LFSR. Algorithmic test pattern generation hardware is often used to minimize the hardware overhead. 2. Response Compressor - is used to compress the large volume of test response. One need to compare the final "compressed words" with the prestored "golden response" to determine the correctness of the circuits. Response Compressor BIST Basics

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**BIST - Goal Reduce input/output pin signal traffic.**

Permit easy circuit initialization and observation. Eliminate as much test pattern generation as possible. Achieve fair fault coverages on general class of failure mode. Reduce test time. Execute at-speed testing. Test circuit during burn-in. The goal of BIST (corresponding to the above statements) 1. if the IC has limited IO pins, the testing can be very difficult because the low testability of the chip. Note, most advanced micro processor has poor testability. Therefore, require BIST simplify the test problem. DFT is another way to improve the testability, discussed in the previous chapter. 2. BIST can be used to initialize the circuit and provide the observability as DFT. 3. With BIST, software test pattern generation can be eliminated virtually. 4. Different from single stuck-at faults for test generation, by the application of exhaustive or pseudoexhaustive patterns, BIST is able to detect all possible faults, or at least, fairly general class of faults such as multiple faults, bridging faults, and the faults you never thing of. 5. Test time is reduced because at--speed testing and without scan (by DFT) 6. Execute at-speed testing testing. It is difficult or expensive by ATE. 7. BIST can be triggered during burn in to remove some faulty chips before the costly test procedure start. Hence, reduce testing time and cost. BIST Basics

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**BIST Issues Area overhead Performance degradation Fault coverage**

Ease of Implementation Capability for system test Diagnosis capability There are several issues we must consider and look into when we applying BIST. 1. The most important factor is the fault coverage. For a highly complicated chip with high profit margin, the overhead of 15-20% is acceptable. Otherwise, 10% of less is more reasonable. 2. Performance degradation due to hardware insertion is another issue. Some time this issue make BIST impossible for high performance (speed) systems. 3. Fault coverage is another important issue. BIST is implemented in systems that require high fault coverage. 4. BIST must be easy to implement because circuit designers are "test idiot". 5. System test is another thing that BIST might have to support. 6. At best, BIST should provide diagnosis capability. BIST Basics

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**BIST Techniques Stored Vector Based**

Microinstruction support Stored in ROM Algorithmic Hardware Test Pattern Generators Counter Linear Feedback Shift Register Cellura Automata BIST techniques has two basic approach 1. Store vector based - Microinstruction supports testing instruction is often seen in stored vector case. It store test program in ROM to trigger BIST routines. Functional testing is most likely here. It often provides diagnosis capability. The most significant disadvantages is hardware overhead of the test Program. 2. Algorithmic hardware - Use algorithmic test hardware to minimize the hardware overhead. For example, counter can generate all possible combinations. Here we will concentrate on linear feedback shift register and cellura automata. BIST Basics - LFSR

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**Linear Feedback Shift Register**

Type 1 Type 2 + D1 D2 D3 D4 D1 D2 D3 D4 + Unit delay - D Flip flop Modulo 2 adder - XOR gate Modulo 2 multiplier -connection LFSR 1. The structure is very simple, it has two types One with exclusive OR gates outside the the shift register loop, type 1. Another one, type 2, has it inside the shift register chain. 2. The linear operators (see the slide) Use the example to show modulo 2 addition and multiplication. We will study the theory part in detail later. BIST Basics - LFSR

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**LFSR - Why? Simple and Regular Structure**

Compatible with scan DFT design Capable of exhaustive and/or pseudo exhaustive testing Low aliasing probability The advantages - 1. Simple and regular structure - as one can see 2. Linear shift register part make it compatible with scan design DFT 3. Can generate all possible combinations except all zero vector. As a result, one can use the vectors for exhaustive and pseudoexhaustive testing. 4. The aliasing probability is 2**-n, n is the order of the characteristic polynomial (will be discussed in detail later). BIST Basics - LFSR

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**LFSR - Recurrence Relation**

... + + + g1 g2 gn-1 D1 D2 D3 Dn-1 Dn ... Is a a-2 a a-n a-n Cs am am-2 am am-n+1 am-n Generating Function Characteristic polynomial Recurrence Relation - 1. Here we want to show that the test vector that a LFSR generate is repetitive with period 2**n -1. 2. Is is the initial status of the LFSR 3. g(s) is the characteristic polynomial, when gi =1, the circle pass the feedback value. 4. Cs is the current status of the LFSR. 5. The sequence generated is represented as G(s) g x i n ( ) = å BIST Basics - LFSR

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**LFSR - Recurrence Relation (continue)**

am = å gi am-i i =1 G(x) = å am xm = å å gi am-i xm = å gi xi å am-i xm-i = å gi xi [a-i x -i a-1 x -1 + åam xm] = å gi xi [a-i x -i a-1 x -1 + G(x)] m=0 n n m=0 i =1 i =1 m=0 n i =1 m=0 n 1. The current polynomial in LFSR 2. G(x) the serial sequence generated in polynomial form 3. Substitute 1 into 2 Take g out of the inner summation equation extract (2) from the inner summation loop Substitute G(x) i =1 BIST Basics - LFSR

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**LFSR - Recurrence Relation (continue)**

1. Reorganize and make it into two summation part 2. Move G(x) to the left hand side. 3. Obtain the relation ship between G(x) and initial status. 4. If initial condition is then the generated sequence G(s) is the inverse of characteristic polynomial g(x) Note that, 1 cannot be divided by g(x) , if g(x) has more than two terms, then, G(x) will have infinite length. G(x) is function of initial state and g(x) BIST Basics - LFSR

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**LFSR Example + D1 D2 D3 D4 BIST Basics - LFSR 1 0 0 0 0 0 0 1 0 0 1 1**

+ D1 D2 D3 D4 Example - 1. The characteristic polynomial is as the one list. 2. The initial condition is 0001 The sequence generated is as follows. You can explain the first few transitions. Pay more attention to D3 xor D0 = Do' 4. Explain that 1 there are all possible combinations except all 0's 2 there are 8 ones in each column 3. there are four runs of 11 in each column 4. there are two runs of 111 in each column 5. there are two runs of 101 in each column Implies there are some interesting properties BIST Basics - LFSR

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LFSR - Definitions If the sequence generated by an n-stage LFSR has period 2n-1, then it is called a maximum-length sequence. The characteristic polynomial associated with maximum-length sequence is called a primitive polynomial. An irreducible polynomial is one that cannot be factored; i.e., it is not divisible by any other polynomial other than 1 and itself. Definitions 1 Maximum-length sequence -- 2**n - 1 2. Primitive polynomial, the one that can generate Msequences 3. Define irreducible polynomial as in the slide 4. Note that, a irreducible polynomial is not necessary a primitive polynomial Example in GF(7) 2 is irreducible but not primitive because 2**n ---> (mod 7) ---> 3 is primitive 3**n ---> (mod 7) ---> BIST Basics - LFSR

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LFSR - Theories If the initial state of an LFSR is a-1=a-2=...= a1-n=0, a-n=1, then the LFSR sequence {am} is periodic with a period that is the smallest integer k for which P(x) divides (1+xk) An irreducible polynomial P(x) satisfies the following two conditions is a primitive polynomial: It has an odd number of terms including the 1 term. If its degree n is greater than 3, then P(x) must divide 1+xk, where k=2n-1 Theories: 1. The theories here is to support the relationship between 1+X**k where k=2**n -1 It can be regarded as another view of "recurrence relation"1 Reason - if 1+x**k divides P(x) then the remainder of 1 divides P(x) is x**k. 2. Continues from the example of previous slide, 2 is not primitive and 3 is primitive, 2 does not have 1 in x**0 (1) BIST Basics - LFSR

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LFSR - Properties The number of 1s in an m-sequence differs from the number of 0s by one. An m-sequence produces an equal number of runs of 1s and 0s. In every m-sequence, one half the runs have length 1, one fourth have length 2, one eighth have length 3, and so forth, as long as the fractions result in integral numbers of runs. Properties 1. Have shown in the previous slides (can go back to the example) there are 8 1s and 7 0s. 2. Use the previous example to show the results. 3. Reiterate the previous example. BIST Basics - LFSR

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**LFSR - Properties (continue)**

M-sequences generated by LFSRs are called pseudo random sequence. The autocorrelation of any output bit is very close to zero. The correlation of any two output bits is very close to zero. 1. Pseudorandom sequence is called because it has the randomness properties list below while there is recurrence relationship of its output sequence. 2. Use the previous example to show (let 1=1 and 0=-1). the inner product of any two columns is equal to 1 3. or the cross correlation is 1/15. (3) BIST Basics - LFSR

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**LFSR - Polynomial Multiplication**

D1 + g1 D2 gn-2 Dn-1 gn-1 Dn gn g0 ... input f(x) output h(x) Now we are going to show that LFSR cab be configurated to implement polynomial multiplication. 1. Multiplication is a shift and add operation. 2. Everytime a clock comes, the LFSR shift one position 3. The incoming bit multiple g(x) 4. The add to the LFSR by xor gate. BIST Basics - LFSR

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**LFSR - Polynomial Multiplication**

D1 D2 D3 + D4 Output stream D4 D3 D2 D1 Input stream x7 x5 x4 x2 1 Example: step by step explanation is given in the example. BIST Basics - LFSR

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**LFSR - Polynomial Division**

g0 g1 gn-2 gn-1 gn D1 D2 Dn-1 Dn ... + + + + input output LFSR used to implement polynomial division 1. Polynomial division is a process of shift and subtract The dividend is the inputs from the right the divider is the characteristic polynomial 2. the subtract is equivalent to add in GF(2) 3. If the most significant bit is 1 the dividend is subtracted by the divider g(x). 4. see the next slide example BIST Basics - LFSR

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**LFSR - Polynomial Division (example)**

Input Output 11001 Q(x) D1 D2 D3 D4 M(x) + + 1+x+x4 x+x2+x4+x5+x7+x8 M(x) D3 D2 D1 D0 Q(x) after 4 shifts Example, The input sequence and characteristic polynomial are as shown x2+x3 1 +x x4 (x8+x7+x5+x4+x2+x) ¸ (x4+x3+1) = x4+x+1 R(x) = x3+x2+1 BIST Basics - LFSR

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**LFSR - Summary LFSRs have two types.**

LFSRs can implement polynomial division and multiplication in GF(2). As polynomial multipliers, LFSRs are capable of generating random vector. As polynomial divisors, LFSRs are capable of compressing test responses. Direct as the slide shows BIST Basics - LFSR

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**Cellura Automata (CA) A One-Dimensional Array of Cells.**

Each cell contains a storage device and next state logic. Next state is a function of current state of the cell and its neighboring cells. Next State Next State Next State Cellura automata 1. It is different from LFSR, LFSR has global feedback loop. CA get information from its neighbors 2. The next state logic is the key component in the CA 3. Three cell neighborhood - Every CA has three inputs 1 itself 2. left neighbor 3. right neighbor D Q D Q D Q Three-Cell Neighbor -- von Newmann Neighborhood BIST Basics - CA

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**Cellura Automata - Name**

Name of CA Functions is determined by its truth table. State A0 A1 A2 A3 A4 A5 A6 A7 Ci+1 Ci Ci-1 Next State KMap FCA A0 A2 A1 A3 A5 A4 A6 A7 (defined by Wolfram) Example: Name = = 102 The NAME or NUMBER of CA comes from its next state truth table. The numbering mechanism is shown in the slide. 1 CiCi-1 Ci+1 1 1 1 BIST Basics - CA

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**Cellura Automata - Hardware**

CA with Null Boundary Condition D Q Fca Hardware, CA with null (0) boundary condition. Standard CA - all the CAs has the same next state logic Hybrid CA - every CA has its own next state logic - can be used to generate weighed random sequence Standard - All the CAs are of the same type Hybrid - The CAs are of different type BIST Basics - CA

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**Cellura Automata - Hardware**

CA with cyclic Boundary Condition D Q Fca D Q Fca D Q Fca Fca Fca Fca D Q D Q D Q Hardware - with feedbacked boundary condition Left most cell - from right most cell Right most cell - from the left most cell TRANSITION - after the theory part lets move on to the hardware for test generation BIST Basics - CA

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**BIST - Pattern Generation**

PG Hardware Stored Patterns Counter Based LFSR Based Cellura Automata Pattern Generated Deterministic Pseudorandom Exhaustive Pseudo exhaustive The pattern generator and patterns being generated can be orthogonal. The candidate test generation hardware include stored patterns (ROM), counter, LFSR, and CA The pattern being generated can be Deterministic, pseudorandom, exhaustive, and pseudoexhaustive Note that, there are techniques to include the generation of deterministic patterns by LFSR. So we separate these two issues. In the following, we will focus on the patterns that are supplied to the CUT to distinguish the BIST techniques. BIST - TestGen

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**TG - Stored Pattern Functional Chip Tests**

Test for structured logic such as ILA Supplemental test for uncovered faults Test control for other methods Architecture support self test command Stored pattern - 1. Mostly stored in ROM 2. Purposes - the items in the slide 3. In most case, the micro instruction much support testing command in order to be cost effective. (do not need too many stored pattern) In other words, the architecture support self test. BIST - TestGen - Stored Pattern

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**Stored Pattern- Supplement for Uncovered faults**

Hard-to-detect faults not covered by random testing hard to detect fault Stored pattern can be used in the case where there are difficult to detect faults 1. Example, the stuck at 0 is difficult to detect because all the inputs must be 1 simultaneously, which is unlikely for random patterns. BIST - TestGen - Stored Pattern

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TG - Counter Based Generates regular test sequences such as walking sequences and counting sequences for memory and interconnect testing Walking Sequence 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Counting Sequence Counter based 1. Used to generate very regular patterns such as Walking sequence - with only one in each row (column) for interconnection network with tri-state testing Counting sequence - every row vector is different for interconnection network testing without tri-state driver row vector - serial vector - applied to a node at different time column vector - parallel vector applied to the network simultaneously BIST - TestGen - Counter Based

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**TG - LFSR Exhaustive Testing Pseudoexhaustive Testing**

Pseudorandom Testing Weighted Pseudorandom Testing LFSR can be used to support and supply the following testing. As the slide shows BIST - TestGen - LFSR

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**TG - Exhaustive Testing**

Apply all possible input combinations A complete functional testing 100% coverage on all possible faults Testing time and hardware overhead are the major considerations for circuits with large number of inputs. LFSR CUT SA Exhaustive testing 1. apply all possible input combinations to the circuit under test. 2. Only by the application of all possible input combinations, the test can be called a complete functional testing. In other words, test by all possible input function. 3. So, it has 100% coverage on all possible faults in the CUT, single and multiple stuck-at faults, shorts of multiple nodes, 3. However, test testing time is 2**n, n is the number of inputs of the CUT BIST - TestGen - LFSR

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**BIST - Pseudo-exhaustive Testing (PET)**

Apply all possible input combination to every partitioned subcircuits. 100% faults coverage on single faults and multiple faults within the subcircuit. Testing time is determined by the number of subcircuits and the number of inputs to the subcircuit. Partitioning is a difficult task. Pseudoexhaustive test - 1. Pseudoexhaustive - exhaustive on submodule and pseudoexhaustive on CUT 2. Partition the CUT into several smaller submodules 3. as 1 in the slide 4. as 2 in the slide 5. give a example for a 40-input circuit, the testing time is 2**40 or 100,000 seconds on 10MHz test clock. If the circuit is partitioned into 10 subcircuits and each have 20 inputs, the testing time is only 1 second. 6. However, partition is a difficult task. Most research emphasize on the partitioning algorithm.

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**TG - PET Hardware Example**

Subcircuit under test MUX L F S R A normal inputs CUT The use of multiplexer for partitioning, proposed by McClusky. 1. Hardware overhead is the major concern here. 2. Fortunately, multiplexers are cheap in CMOS technology 3. The overhead on wiring may cause more silicon area than gates. 4. Performance degradation is another concern. BIST - TestGen - LFSR

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**BIST - Pseudo Random Testing**

Apply random test sequence generated by LFSR/CA. Simplest to design and implement Lowest in hardware overhead Fault coverage is a function of the test length and the testability of the circuits Pseudorandom testing 1. as the slide 1-4 2. One concern on this technique is the fault coverage. Hard to detect faults is the major concern here. 3. We will show the relationship among, testability, fault coverage, and testing time in the next slide. 4. Research on this topic emphasize on how to improve test vector efficiency and how to embedded deterministic vectors in the pseudorandom sequences. BIST - TestGen - LFSR

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**BIST - Pseudo Random Testing Hardware**

Combinational Sequential LFSR Combinational circuit SA Pseudorandom testing hardware structure - 1. There are for combinational circuits and for sequential circuits. 2. For sequential circuits, some called it circular BIST because the contents of internal memory cells are recycled as test vectors. 3. There are different test vector generators and signature analyzer structure We will discuss that later. (BEST) (Circular BIST) BIST - TestGen - LFSR

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**BIST - Pseudo Random Testing Hardware**

LFSR Shift register LFSR Circuit Under Test S R S R S R CUT CUT SA SA Some alternative 1. Use shift register to replace some LFSR stages to reduce hardware overhead 2. CEBT will be discussed later. 3. For sequential circuits, the internal flip-flops are connected as shift register. And, the shift registers are connected to LFSR and SA. 4. Stumpt can be configured as combinational testing, shift out all the contents of SR, sequential BIST(CBIST), one test per clock. (CEBT) (STUMPS) BIST - TestGen - LFSR

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**Pseudo Random Test Length**

eth: Escape Threshold gmin: the detection probability of the hardest to detect fault by a random vector k: the number of faults with detection probability 2gmin Example 1: eth=0.001, gmin=1E-5, k=5 * m=851,716 Example 2: eth=0.001, gmin=1E-5, k=50 * m=1,081,973 Pseudorandom testing test length determination 1. Escape threshold - the portion of fault that you allow to be missed in the test 2. The minimum detection probability of the hardest to detect faults. For example, for a mere 4-input and gate, the g_min is 1/16 for output stuck-at-0. 3. K the number of faults with detection probability between g_min and 2g_min 4. By Markov model, the equation is derived as the slide 5. Examples BIST - TestGen - LFSR

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**BIST - Weighted Pseudo Random Test**

LFSR Based Weighted Celluar Automaton D Q 123 193 61 114 228 92 25 LFSR 1/8 3/4 1/2 7/8 Weighted pseudorandom test 1. Random pattern has low testability because there are many random pattern resistant faults such as the output of an and gate tree. 2. One way to cope the problem is to change the probability of 1s or weights of each inputs. 3. For LFSR, one can use logic gates to change the weight. Example, as shown in the slide 4. for CA, with the hybrid structure, cells of different types, one can change the weights of each inputs. However, it is difficult to determine the weights. Example, as the slide. BIST - TestGen - LFSR

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**BIST - Response Compression**

Introduction Ones-Count Compression Transition-Count Compression Syndrome-Count Compression Signature Analysis Space Compression Response Compression As the slide The above methods, ones count, ... signature analysis, are time compression. We will introduce a space compression technique. BIST - ResComp

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**BIST - Response Compression**

Bit-to-bit Comparison is infeasible for BIST. Compress a very long output sequence into a single signature. Compare the compressed word with the prestored gold signature to determine the correctness of the circuit. Many output sequences may have the same signature after the compression, the aliasing problem. Poor diagnosis resolution after compression. Response compression - Why do we need response compression 1. stored response for compression is very costly 2. as the slide 3. as the slide 4. Compression is like a function which map a large input space (the response) into a small out space (single space). Therefore, it is a n-to-1 mapping. Therefore, a faulty response may has the same signature as the fault-free output sequence. In this case, we called it, aliasing. 5. It is unlikely to do diagnosis after compression. Because the responses are scrambled and skewed after compression. BIST - ResComp

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**Ones-Count - Hardware Apply predetermined patterns**

Count the number of ones in the output sequence. Test Pattern CUT Counter Clock Ones-count 1. Apply a sequence of predetermined patterns. The pattern can be deterministic pattern generated by ATPG or pseudorandom, exhaustive, or pseudoexhaustive pattern generated by LFSR. One thing must be certain is that, the patterns used in fault simulation are the same as those applied. 2. It count the number of ones in the output sequence. 3. The figure show a single output CUT. For multiple output CUT, it must has either multiple counters or one counter and a multiplexer to count the ones of each output one by one. 4. Give a small example BIST - ResComp

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**Ones Counter - Aliasing**

Aliasing Probability m: the test length r: the number of ones r=m/2, the case with the highest aliasing probability r=m and r=0, no aliasing probability For combinational circuits, the input sequence can be permuted without changing the count. Ones Count - Discussion 1. Aliasing probability - as shown The denominator is the total number of faulty output combinations only one good output sequence. 2**m is all possible output sequences. The numerator is the total number of sequences that has r ones, the same as the fault-free sequence. 2. as the slide 3. as the slide In order to lower the aliasing probability, one can select the test vectors that have as many (or fewer) output ones as possible. 4. For combinational circuits, the input sequence can be changed but the test set must be the same. BIST - ResComp

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**Transition Count Apply predetermined patterns**

Count the number of the transitions (0 *1 and 1 *0) Test Pattern CUT Counter Clock DFF Transition count 1. Similar to ones count, it counts the number of transitions from one to zero and/or from zero to ones. 2.The circuit shows the circuit to detect both 1-to-0 and 0-to-1 transitions. 3. Similarly, the patterns applied must be the same as those used in fault simulation. BIST - ResComp

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Transition Count Aliasing Probability m: the test length r: the number of transitions r=m/2, highest aliasing probability. r=0 and r=m , no aliasing probability For combinational circuits, the input sequence cannot be permuted. One can reorder the test sequence to minimize the aliasing probability. Transition count - 1. Aliasing probability Denominator - The same as the ones count. Numerator - the combinations of r transitions selected from m-1 possible transition position. Since that the first transition can be from 1-to-0 or from 0-to-1. So, 2 is put it here. The 1 in the numerator is the correct sequence. 2. as the slide 3. the input sequence must be exactly the same as those used in the fault simulation. If you change the order of the application sequence, the number of transitions will be changed. 4. However, one can reorder the test sequence to have only one transitions to minimize the transition probability. BIST - ResComp

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**Syndrome Testing Apply random patterns. Count the probability of 1.**

The property is similar to that of ones count. random test pattern CUT Syndrome counter Counter / Clock Syndrome Syndrome testing 1. Similar to ones count. However, it calculates the probability of ones of the output sequence instead of the exact number of 1s. 2. Therefore, it does not require that the patterns must be the same. One only need to apply a set of random patterns with certain randomness properties. 3. The test sequence must be very long in order to minimize the ambiguity. 4. The number of patterns that are needed can be determined by the large number theory in the probability theories. BIST - ResComp

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**Signature Analysis Apply predetermined test patterns.**

Divide the Output Sequence by LFSR. CUT Test Pattern LFSR Signature analysis 1. Use the division property of LFSR to accomplish compression. 2. It divides the output sequence by the characteristic polynomial. 3. The remainder is the signature. 4. The input sequence must be predetermined. BIST - ResComp

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Signature Analysis Aliasing Probability m: test length, n: length of LFSR Aliasing probability is output independent. An LFSR with two or more nonzero coefficient detect any single faults. An LFSR with primitive polynomial detect any double faults separated less than 2n-1 An LFSR with g0=1 detects all burst error of length less than n. LFSR - In the following, we use the e(x) to represent the faults, the aliasing will occur if e(x) can be divided evenly by g(x). In this case, the faulty sequence and fault-free sequence will have the same signature. 1. Aliasing probability, the denominator is the all possible faulty output sequence, the numerator is the output sequence that have the same remainder (signature) as the fault-free one. 2. If there is only one fault, the error polynomial x**n will not divide g(x) of two or more terms (remember the recurrence relation) 3. x**k-1 cannot divide g(x) if k is less than 2**n 4. e(x) of order less than n cannot divide g(x) BIST - ResComp

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**Multiple Input Signature Register (MISR)**

type 1 D4 + D3 D2 D1 D4 + D3 D2 D1 type 2 Multiple Input Signature Register (MISR) (pronounced MYSER) 1. The multiple inputs are feed to the XOR gates before the flip-flop. 2. The property is similar to LFSR. BIST - ResComp

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Space Compression Use space compression to handle large output circuits. Use XOR gates to compress space. Use Error Control Coding to achieve better fault coverage. Example: A 16 SEC-DED code compresses 16 outputs into 5. 1 2 3 4 5 6 7 8 + 9 10 11 12 13 14 15 16 P1 P2 P3 P4 P5 Space Compression - 1. as the slide says BIST - ResComp

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**BIST - Space and Time Compression**

CUT TC SC CUT TC SC Space-Time Compression Time-Space Compression The combination of space compression and time compression 1. Time compression - for large volume of test responses 2. Space compression - for large number of output pins. 3. We can do space compression first then time compression or vise versa. However the effect may be different. BIST - ResComp

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**BIST Examples HP Focus Chip, Functional Chip Test**

Built-in Logic Block Observation (BILBO) [Koenemann 79] Centralized and Separate Board Level BIST (CSBL) [Benowitz 75] Built-in Evaluation and Self-Test (BEST) [Resnick 83] Random-Test Socket (RTS) [Bardell 82] LSSD On-Chip Self Test (LOCST) [LeBlanc 84] Self test using MISR and Parallel SRSG (STUMPS) [Bardell 82] BIST - Example

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**BIST Examples (cont.) Concurrent BIST Architecture (CBIST) [Saluja 88]**

Centralized and Embedded BIST with Boundary Scan (CEBS) Random Test Data (RTD) [Bardell 87] Simultaneous Self Test (SST) [Gupta 82] Cyclic Analysis Testing System (CATS) [Burkness 87] Circular Self-Test Path (CSTP) [Krasniewski 89] BIST - ResComp

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**BIST - HP Focus Chip (Stored Pattern)**

Chip Summaries 450,000 NMOS devices, 300,000 Nodes 24MHz Clocks, 300K bits of on-chip ROM Used in HP computer BIST Microprogram Use microinstructions dedicated for testing 100K-bit BIST microprogram in CPU ROM Executes 20 million clock cycles Greater than 95% stuck-at coverage A power-up test used in system test, filed test, and wafer test BIST - Example

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**BIST - BILBO Built-in Logic Block Observation [Koenemann 79.80]**

1 MUX Z1 Q D Q1 Z2 Q2 ... Qn-1 Zn Qn S0 Si B2 B1 C1 BILBO1 BILBO2 C2 BILBO3 C3 B1 B2 BILBO 0 0 shift register 0 1 reset 1 0 MISR (input * constant * LFSR) 1 1 parallel load (normal operation) BIST - Example

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**BIST - CSBL Centralized and Separate Board-Level BIST [Benowitz 75]**

Use only one Signature Register Tests repeat m times to reduce hardware cost CUT (C or S) MUX SISR Counter PRPG n k 1 m PIs POs BIST - Example

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**BIST - BEST Built - Evaluation and Self Test [Resnick 83]**

Pseudo random testing Hardware overhead is low Test length can be long for CUT with random-pattern resistant faults. PRPG CUT (C or S) MISR PI PO BIST - Example

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**BIST - RTS Random-Test socket [Bar dell 82]**

Combine LSSD Scan Chain and BIST Can insert test points to reduce test length for random-pattern resistant faults CUT (S) Sin Sout Clocks Controls PRPG MISR SRSG R1 R3 R2 SISR R4 BIST controller BIST - Example

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**Error-detection circuitry**

BIST - LOCST LSSD On-Chip Self-Test [LeBlanc 84] Boundary scan is required to unify the test architecture Single scan chain may cause high test time overhead. CUT (S) Si S0 SRSG PIs SRL R1 SISR POs R2 On-chip monitor (OCM) Error-detection circuitry Sin Error signal Control signals BIST - Example

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**BIST - STUMPS Self-Test using MISR and Parallel SRSG [Bardell 82,84]**

Multiple scan chain to reduce test time ... PIs POs PRPG Scan path . . . CUT (S) So So* External logic BIST - Example

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**BIST - CBIST Concurrent Built-in Self Test [Saluja 88]**

Comparator PRPG MUX N / T Normal inputs CUT (C) MISR Normal outputs EN CBIST Circuitry Concurrent Built-in Self Test [Saluja 88] Detect test patterns from normal inputs sequence Once a pattern is detected, compress the response and tick the test clock. If waited too long, insert a test pattern from PRPG. BIST - Example

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**Boundary-scan register**

BIST - CEBS Centralized and Embedded BIST architecture with Boundary Scan [Komanytsky 82.83] A low cost version of RTS or LOCST CUT (S) Si So Boundary-scan register Input . . . Output PIs POs RPG (PRPG/SRSG) SR (MISR/SISR) Sin Sout BIST - Example

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**BIST - RTD Random Test Data [Bazdell 87]**

Use MISR to replace internal storage devices for test generation and response comparison C MISR . . . PRPG ... Sin Sout PIs POs R1 R3 R2 CUT BIST - Example

63
**BIST - SST Simultaneous Self Test [Gupta 82]**

Similar to MISR but without LFSR part PI CUT Combinational PO BIST - Example

64
**BIST - CATS Cyclic Analysis Test System [Burkness 87]**

If more outputs than inputs, space compression is needed. If less outputs than inputs, an output drive multiple inputs. A synchronous feedback loops can be created, therefore may create races. S x1 xn . . . z1 zn ... MUX N / T Original Circuit BIST Circuit x1 BIST - Example

65
**BIST - CSTP Circular Self Test Path [Krasniewski 89]**

- conventional register - self-test path register POs PIs Key C . . . z1 z2 zm x1 x2 xm Circular Self Test Path [Krasniewski 89] Similar to SST except that boundaries are scanned Not all registers are self-test path registers. BIST - Example

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**BIST - PLA General Structure**

AND Plane First NOR Plane OR Plane Second NOR Plane . product lines . . . . . . Input Decoders Output Buffers . . . . . . PLA Inputs PLA Outputs BIST - PLA

67
**BIST - PLA Circuit Structure**

Vdd Vdd p1 p2 p3 Input Decoders Output Buffer x1 x2 x3 z1 z2 BIST - PLA

68
**BIST PLA - Fault Model Stuck-at faults (A) Bridging faults (B)**

AND OR Stuck-at faults (A) Bridging faults (B) Cross Point faults Missing Device fault (C) Extra Device faults (D) A D C B BIST - PLA

69
**BIST PLA - Cross Point faults**

Growth - The missing device in AND plane causes an input variable to disappear from a product term. Shrink - The extra device in AND plane causes an input variable to appear in a implicant. Disappearance - The missing device in OR plane causes an implicant to disappear from a function. Appearance - The extra device in OR plane causes an implicant to appear in a function. BIST - PLA

70
**PLA Testing Test generation is difficult for large PLAs**

- Pseudorandom resistance due to large fan-ins Easily testable designs - Add moderate hardware overhead to make pattern generation easier - The general idea is to make each product line controllable and observable Built-In Self Test - A varieties of technique were proposed - The effectiveness is evaluated by Hardware overhead Test length Delay per test application

71
**The HJA Scheme Proposed by Hua, Jou and Abraham**

Solve pitch mismatch problem by using multiplexing in the Augmented Decoder Hardware Overhead: fair - AD, TPG, PC2 and PC3 Test length: good - 2M+P+2 Delay per test application: fair -Limited by the parity checkers

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**The HJA Scheme (continue)**

Inputs Feedback Lines Output Cells PC3 TPG Interface Cells OR Array AND Array E2 PC2 Outputs TPG: Test Pattern Generator AD: Augmented Decoder PC: Parity Checkers AD

73
**TFA Scheme Proposed by Treuer, Fujiwara and Agarwal**

Hardware overhead: good - AD, PS, PC3 Test length: fair - 2MP + 2M + 1 Delay per test application: fair - Limited by the parity checker

74
**TFA Scheme (continue) E3 C2 C1 Inputs Feedback Lines Output Cells PC3**

Interface Cells OR Array AND Array Outputs AD Sin PS: Product Line Selector PS

75
**HM Scheme Proposed by Hassan and McCluskey Hardware overhead: bad**

- A M-bit LFSR generates exhaustive patterns - Three LFSRs compress the results Test length: bad - Bad for PLAs with large number of inputs Delay per test application: good - Use signature analyzer instead of parity checkers

76
**HM Scheme (continue) L L AND Array OR Array G LS**

Complemented Bit Lines L True Bit Lines AND Array OR Array Inputs Output G LS G: Maximum Length Sequence Generator L: Parallel LFSR LS: LFSR(s) Used to Compact the Outputs

77
**DM Scheme Proposed by Daehn and Mucha**

Using nonlinear feedback shift registers for both pattern generation and response compression Hardware overhead: bad - Three slightly modified BILBOs Test length: good - 2M + P + Q + 1 Delay per test application: good

78
**DM Scheme (continue) BIST - PLA BILBO2 AND Plane OR Plane BILBO1**

Input Decoders Input Decoders BIST - PLA

79
**The New BIST Design Hardware overhead: good - AD, PS and MISR**

Test length: fair - 2MP Delay per test application: good - No parity checkers

80
**The New BIST Design (continue)**

Inputs Feedback Lines Interface Cells OR Array AND Array Outputs AD: Augmented Decoder PS: Product Line Selector MISR: Multiple Input Signature Register G(X): Characteristic Polynomial AD PS Sin MISR G(X) = XQ+1 Sout C2 E2 E1

81
The New BIST Design Use AD and PS to evaluate each device in the AND array Use MISR with XQ + 1 as the characteristic polynomial - Hardware complexity is comparable to that of the parity checker Add one extra input - Make the product lines of the AND array all have an odd number of devices and an odd number of nondevices Add one or two product lines - Make the bit lines of the AND array all have an odd number of devices - Make the output lines all have an odd number of devices - Make the PLA have an odd number of product lines

82
**Fault Coverage 1 1 MISR with XQ + 1 1 1 1 1 1**

Si(x) = 1 + x + x2 + x4 = 11101 Ri(x) = x + x2 = 01100 1 1 1 1 1 1 1 Si+1(x) = 1 + x3 = 10010 In order to guarantee the detection of all modeled faults, the E(X) caused by some fault must satisfy the requirement of E(X) mod XQ + 1 ¹ 0

83
Fault Coverage Theorem 1: E(X) mod XQ + 1 ¹ 0 if E(X) has an odd number of terms Theorem 2: All the single contact faults and stuck at faults cause E(X) to have an odd number of terms in the BIST design Theorem 3: R(X) mod XQ +1 has an odd number of terms if R(X) has an odd number of terms Corollary 1: F(X) mod XQ + 1 has an even number of terms if F(X) has an even number of terms Parity of fault-free signature is 1

84
**Fault Coverage Parity of faulty signature is 0**

Short faults between two adjacent bit lines are detected by NOR gate E1 Short faults between two adjacent product lines are detected by the NOR gate E2 combined with a parity counter Short faults between two adjacent output are not 100% detectable

85
Conclusion Deterministic test pattern generation is used to generate the efficient test patterns The simplest MISR is used to compress the results into only ONE bit The final signature can be further compressed into only ONE bit All the single stuck-at faults and contact faults are detected The design gives a better trade-off between the cost and the performance of BIST PLAs

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Princess Sumaya University

Princess Sumaya University

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