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Built-in Self-test

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**Introduction Test generation and response evaluation done on-chip.**

Only a few external pins to control BIST operation. Additional hardware overhead. Offers a number of benefits.

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**BIST Motivation Useful for field test and diagnosis:**

Less expensive than a local automatic test equipment Software tests for field test and diagnosis: Low hardware fault coverage Low diagnostic resolution Slow to operate Hardware BIST benefits: Lower system test effort Improved system maintenance and repair Improved component repair Better diagnosis

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**BIST – Basic Idea CHIP Test Generator Circuit Under Test (CUT)**

The basic structure of BIST include two extra modules. 1. Test pattern generator to generate desired test vectors. The possible generators include ROM, counters and LFSR. Algorithmic test pattern generation hardware is often used to minimize the hardware overhead. 2. Response Compressor - is used to compress the large volume of test response. One need to compare the final "compressed words" with the prestored "golden response" to determine the correctness of the circuits. Response Compressor

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**BIST Architecture TEST TEST CONTROLLER M Circuit U under X = test**

ROM M U X Circuit under test Pattern Generator Response Compactor = Good / Bad PI PO Note: BIST cannot test wires and transistors: From PI pins to input MUX From POs to output pins

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**BIST Costs Chip area overhead for: Test controller**

Hardware pattern generator / response compactor Testing of BIST hardware Pin overhead At least 1 pin needed to activate BIST operation Performance overhead Extra path delays due to BIST

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Yield loss Due to increased chip area Reliability reduction Due to increased area Increased BIST hardware complexity Happens when BIST hardware is made testable

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**BIST Benefits Faults tested: BIST benefits**

Single combinational / sequential stuck-at faults Delay faults Single stuck-at faults in BIST hardware BIST benefits Reduced testing and maintenance cost Lower test generation cost Reduced storage / maintenance of test patterns Simpler and less expensive ATE Can test many units in parallel Shorter test application times Can test at functional system speed

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**BIST Techniques Stored Vector Based**

Microinstruction support Stored in ROM Algorithmic Hardware Test Pattern Generators Counter :: exhaustive, pseudo-exhaustive Linear Feedback Shift Register Cellular Automata BIST techniques has two basic approach 1. Store vector based - Microinstruction supports testing instruction is often seen in stored vector case. It store test program in ROM to trigger BIST routines. Functional testing is most likely here. It often provides diagnosis capability. The most significant disadvantages is hardware overhead of the test Program. 2. Algorithmic hardware - Use algorithmic test hardware to minimize the hardware overhead. For example, counter can generate all possible combinations. Here we will concentrate on linear feedback shift register and cellura automata.

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**Exhaustive Pattern Generation**

Shows that every state and transition works For n-input circuits, requires all 2n vectors Impractical for n > 20

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**Pseudo-Exhaustive Method**

Partition large circuit into fanin cones Backtrace from each PO to PIs influencing it Test fanin cones in parallel An illustrative example (next slide): No. of tests reduced from 28 = 256 to 25 x 2 = 64

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**Pseudo-Exhaustive Pattern Generation**

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**Random Pattern Testing**

Generate pseudo-random patterns as test input vectors. Evaluate fault coverage through fault simulation. Motivation: Test length may be larger. Faster test generation. Used to get tests for 60-80% of faults, then switch to ATPG for rest. Some circuits may be random pattern resistant.

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100% % Fault Coverage Number of test vectors

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P R P G C U T Response Evaluation

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**Linear Feedback Shift Register (LFSR)**

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**What is LFSR? A simple hardware structure based on shift register.**

Linear feedback circuit. Has a number of useful applications: Pseudo-random number generation Response compression Error checking (Cyclic Redundancy Code) Data compression

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**Two types of LFSR Type 1 Type 2 + D1 D2 D3 D4 D1 D2 D3 D4 + Unit delay**

D Flip flop Modulo 2 adder XOR gate Modulo 2 multiplier Connection LFSR 1. The structure is very simple, it has two types One with exclusive OR gates outside the the shift register loop, type 1. Another one, type 2, has it inside the shift register chain. 2. The linear operators (see the slide) Use the example to show modulo 2 addition and multiplication. We will study the theory part in detail later.

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General Type-1 LFSR

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LFSR Example + D1 D2 D3 D4 Example - 1. The characteristic polynomial is as the one list. 2. The initial condition is 0001 The sequence generated is as follows. You can explain the first few transitions. Pay more attention to D3 xor D0 = Do' 4. Explain that 1 there are all possible combinations except all 0's 2 there are 8 ones in each column 3. there are four runs of 11 in each column 4. there are two runs of 111 in each column 5. there are two runs of 101 in each column Implies there are some interesting properties

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**LFSR - Recurrence Relation**

... + + + g1 g2 gn-1 D1 D2 D3 Dn-1 Dn ... IS: a a-2 a a-n a-n CS: am am-2 am am-n+1 am-n Generating Function Characteristic polynomial Recurrence Relation - 1. Here we want to show that the test vector that a LFSR generate is repetitive with period 2**n -1. 2. Is is the initial status of the LFSR 3. g(s) is the characteristic polynomial, when gi =1, the circle pass the feedback value. 4. Cs is the current status of the LFSR. 5. The sequence generated is represented as G(s) f x c i n ( ) = å 1 + 1

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**LFSR - Recurrence Relation (contd.)**

am = å ci am-i i =1 G(x) = å am xm = å å ci am-i xm = å ci xi å am-i xm-i = å ci xi [a-i x -i a-1 x -1 + åam xm] = å ci xi [a-i x -i a-1 x -1 + G(x)] m=0 n n m=0 i =1 i =1 m=0 n i =1 m=0 1. The current polynomial in LFSR 2. G(x) the serial sequence generated in polynomial form 3. Substitute 1 into 2 Take g out of the inner summation equation extract (2) from the inner summation loop Substitute G(x) n i =1

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**LFSR - Recurrence Relation (contd.)**

1. Reorganize and make it into two summation part 2. Move G(x) to the left hand side. 3. Obtain the relation ship between G(x) and initial status. 4. If initial condition is then the generated sequence G(s) is the inverse of characteristic polynomial g(x) Note that, 1 cannot be divided by g(x) , if g(x) has more than two terms, then, G(x) will have infinite length. G(x) is function of initial state and g(x)

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LFSR - Definitions If the sequence generated by an n-stage LFSR has period 2n-1, then it is called a maximum-length sequence or m-sequence. The characteristic polynomial associated with maximum-length sequence is called a primitive polynomial. An irreducible polynomial is one that cannot be factored; i.e., it is not divisible by any other polynomial other than 1 and itself. Definitions 1 Maximum-length sequence -- 2**n - 1 2. Primitive polynomial, the one that can generate Msequences 3. Define irreducible polynomial as in the slide 4. Note that, a irreducible polynomial is not necessary a primitive polynomial Example in GF(7) 2 is irreducible but not primitive because 2**n ---> (mod 7) ---> 3 is primitive 3**n ---> (mod 7) --->

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**Example Primitive Polynomials**

3: x3 + x + 1 4: 5: 6: 7: 8: 16: 32: 64:

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**LFSR - Theories If the initial state of an LFSR is**

a-1 = a-2 = ... = a1-n = 0, a-n = 1 then the LFSR sequence {am} is periodic with a period that is the smallest integer k for which f(x) divides (1+xk). An irreducible polynomial f(x) satisfying the following two conditions is a primitive polynomial: It has an odd number of terms including the 1 term. If its degree n is greater than 3, then f(x) must divide (1 + xk), where k = 2n–1 Theories: 1. The theories here is to support the relationship between 1+X**k where k=2**n -1 It can be regarded as another view of "recurrence relation"1 Reason - if 1+x**k divides P(x) then the remainder of 1 divides P(x) is x**k. 2. Continues from the example of previous slide, 2 is not primitive and 3 is primitive, 2 does not have 1 in x**0 (1)

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**Properties of m-sequences**

The period of {an} is p=2n-1, that is, ap+I = ai, for all i 0. Starting from any nonzero state, the LFSR that generates {an} goes through all 2n-1 states before repeating. The number of 1’s differs from the number of 0’s by one. If a window of width n is slid along an m-sequence, then each of the 2n-1 nonzero binary n-tuples is seen exactly once in a period. In every period of an m-sequence, one-half the runs have length 1, one-fourth have length 2, one-eighth have length 3, and so on.

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**Randomness Properties of m-sequence**

m-sequences generated by LFSRs are called pseudo random sequence. The autocorrelation of any output bit is very close to zero. The correlation of any two output bits is very close to zero. 1. Pseudorandom sequence is called because it has the randomness properties list below while there is recurrence relationship of its output sequence. 2. Use the previous example to show (let 1=1 and 0=-1). the inner product of any two columns is equal to 1 3. or the cross correlation is 1/15. (3)

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**LFSR as Pseudo-Random Pattern Generator**

Standard LFSR Produces patterns algorithmically – repeatable. Has most of desirable randomness properties. Need not cover all 2n input combinations. Long sequences needed for good fault coverage.

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**Weighted Pseudo-Random Pattern Generation**

s-a-0 F 1 256 If p (1) at all PIs is 0.5, pF (1) = = Will need enormous # of random patterns to test a stuck-at 0 fault on F. We must not use an ordinary LFSR to test this. IBM holds patents on weighted pseudo-random pattern generator in ATE. 1 256 255 256 pF (0) = 1 – =

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**Need 2-3 weight sets for a typical circuit. **

LFSR p (1) = 0.5 Solution: Add programmable weight selection and complement LFSR bits to get p (1)’s other than 0.5. Need 2-3 weight sets for a typical circuit. Weighted pattern generator drastically shortens pattern length for pseudo- random patterns.

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**Weighted Pattern Generator**

w2 1 Inv. p (output) 3/4 1/8 7/8 1/16 15/16

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**How to compute weights? Assume p(1) of primary output(s) to be 0.5.**

Systematically backtrace and compute the p(1) values of all other lines. Finally obtain the p(1) values of the primary input lines.

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**Cellular Automata (CA)**

Superior to LFSR – even “more” random No shift-induced bit value correlation Can make LFSR more random with linear phase shifter Regular connections – each cell only connects to local neighbors xc-1 (t) xc (t) xc+1 (t) Gives CA cell connections xc (t + 1) = 90 Called Rule 90 xc (t + 1) = xc-1 (t) xc+1 (t)

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**Cellular Automata Example**

Five-stage hybrid cellular automaton Rule 150: xc (t + 1) = xc-1 (t) xc (t) xc+1 (t) Alternate Rule 90 and Rule 150 CA

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**Test Pattern Augmentation**

Secondary ROM – to get LFSR to 100% stuck-at fault coverage. Add a small ROM with missing test patterns. Add extra circuit mode to input MUX – shift to ROM patterns after LFSR done. LFSR reseeding is another alternative. Use diffracter: Generates cluster of patterns in neighborhood of stored ROM pattern. Transform LFSR patterns into new vector set. Put LFSR and transformation hardware in full-scan chain.

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**Test Response Compaction**

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**Response Compaction Huge volume of data in CUT response:**

An example: Generate 5 million random patterns CUT has 200 outputs Leads to: 5 million x 200 = 1 billion bits response Uneconomical to store and check all of these responses on chip. Responses must be compacted.

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**Definitions Aliasing Compaction Compression**

Due to information loss, signatures of good and some bad circuits match. Compaction Drastically reduce # bits in original circuit response. Loss of information. Compression Reduce # bits in original circuit response . No information loss – fully invertible (can get back original response).

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**Ones Count (Syndrome) Compaction. Transition Count Response Compaction**

Signature analysis Compact good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature. Ones Count (Syndrome) Compaction. Count # of 1’s Transition Count Response Compaction Count # of transitions from 0 1 and 1 0 as a signature.

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**BIST - Response Compression**

Introduction Ones-Count Compression Transition-Count Compression Syndrome-Count Compression Signature Analysis Space Compression Response Compression As the slide The above methods, ones count, ... signature analysis, are time compression. We will introduce a space compression technique.

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**Some Points Bit-to-bit comparison is infeasible for BIST.**

General principle: Compress a very long output sequence into a single signature. Compare the compressed word with the prestored golden signature to determine the correctness of the circuit. Problem of aliasing: Many output sequences may have the same signature after the compression. Poor diagnosis resolution after compression.

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**Ones-Count - Hardware Apply predetermined patterns.**

Count the number of ones in the output sequence. CUT Test Pattern Ones-count 1. Apply a sequence of predetermined patterns. The pattern can be deterministic pattern generated by ATPG or pseudorandom, exhaustive, or pseudoexhaustive pattern generated by LFSR. One thing must be certain is that, the patterns used in fault simulation are the same as those applied. 2. It count the number of ones in the output sequence. 3. The figure show a single output CUT. For multiple output CUT, it must has either multiple counters or one counter and a multiplexer to count the ones of each output one by one. 4. Give a small example Clock Counter

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**Ones Counter - Aliasing**

Aliasing Probability m : the test length r : the number of ones r=m/2 :: the case with the highest aliasing prob. r=m and r=0 :: no aliasing probability For combinational circuits, the input sequence can be permuted without changing the count. Ones Count - Discussion 1. Aliasing probability - as shown The denominator is the total number of faulty output combinations only one good output sequence. 2**m is all possible output sequences. The numerator is the total number of sequences that has r ones, the same as the fault-free sequence. 2. as the slide 3. as the slide In order to lower the aliasing probability, one can select the test vectors that have as many (or fewer) output ones as possible. 4. For combinational circuits, the input sequence can be changed but the test set must be the same.

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**Transition Count - Hardware**

Apply predetermined patterns Count the number of the transitions (0 1 and 1 0). DFF CUT Test Pattern Transition count 1. Similar to ones count, it counts the number of transitions from one to zero and/or from zero to ones. 2.The circuit shows the circuit to detect both 1-to-0 and 0-to-1 transitions. 3. Similarly, the patterns applied must be the same as those used in fault simulation. Clock Counter

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**Transition Count Aliasing Probability**

m : the test length r : the number of transitions r=m/2 :: highest aliasing probability r=0 and r=m :: no aliasing probability Transition count - 1. Aliasing probability Denominator - The same as the ones count. Numerator - the combinations of r transitions selected from m-1 possible transition position. Since that the first transition can be from 1-to-0 or from 0-to-1. So, 2 is put it here. The 1 in the numerator is the correct sequence. 2. as the slide 3. the input sequence must be exactly the same as those used in the fault simulation. If you change the order of the application sequence, the number of transitions will be changed. 4. However, one can reorder the test sequence to have only one transitions to minimize the transition probability.

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**To maximize fault coverage:**

Transition count: C (R) = (ri ri-1) for all m primary outputs To maximize fault coverage: Make C (R0), good machine transition count, as large or as small as possible m i = 1

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**Syndrome Testing Apply exhaustive test patterns.**

Count the number of 1’s in the output. Normalize by dividing with number of minterms. CUT counter Syndrome testing 1. Similar to ones count. However, it calculates the probability of ones of the output sequence instead of the exact number of 1s. 2. Therefore, it does not require that the patterns must be the same. One only need to apply a set of random patterns with certain randomness properties. 3. The test sequence must be very long in order to minimize the ambiguity. 4. The number of patterns that are needed can be determined by the large number theory in the probability theories. Clock Syndrome counter

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**Analysis of Syndrome Testing**

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**Signature Analysis Apply predetermined test patterns.**

Compress the output sequence by LFSR. Compressed value is called signature. CUT Test Pattern LFSR Signature analysis 1. Use the division property of LFSR to accomplish compression. 2. It divides the output sequence by the characteristic polynomial. 3. The remainder is the signature. 4. The input sequence must be predetermined.

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**Signature Analysis Aliasing Probability**

m: test length, n: length of LFSR Aliasing probability is output independent. An LFSR with two or more nonzero coefficients detect any single faults. An LFSR with primitive polynomial detect any double faults separated less than 2n-1. LFSR - In the following, we use the e(x) to represent the faults, the aliasing will occur if e(x) can be divided evenly by g(x). In this case, the faulty sequence and fault-free sequence will have the same signature. 1. Aliasing probability, the denominator is the all possible faulty output sequence, the numerator is the output sequence that have the same remainder (signature) as the fault-free one. 2. If there is only one fault, the error polynomial x**n will not divide g(x) of two or more terms (remember the recurrence relation) 3. x**k-1 cannot divide g(x) if k is less than 2**n 4. e(x) of order less than n cannot divide g(x)

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**LFSR Based Response Compaction**

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**LFSR for Response Compaction**

Use LFSR based CRC generator as response compacter. Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial. CRC divides the PO polynomial by its characteristic polynomial. Leaves remainder of division in LFSR. Must initialize LFSR to seed value (usually 0) before testing. After testing – compare signature in LFSR to known good machine signature. Critical: Must compute good machine signature.

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**Example Modular LFSR Response Compacter**

LFSR seed value is “00000”

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**Polynomial Division Inputs Initial State 1 X0 1 X1 1 X2 1 X3 1 X4 1**

X0 1 X1 1 X2 1 X3 1 X4 1 Logic Simulation: Logic simulation: Remainder = 1 + x2 + x3 Input polynomial: x1 + x3 + x7

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**Symbolic Polynomial Division**

x2 x7 + 1 + x5 x5 x5 + x3 + x + 1 + x3 x3 + x + x2 + 1 remainder Remainder matches that from logic simulation of the response compacter!

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**Multiple-Input Signature Register (MISR)**

Problem with ordinary LFSR response compacter: Too much hardware if one of these is put on each primary output (PO). Solution: MISR – compacts all outputs into one LFSR Works because LFSR is linear – obeys superposition principle. Superimpose all responses in one LFSR. Final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial.

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**Multiple Input Signature Register (MISR)**

D4 + D3 D2 D1 type 1 D4 + D3 D2 D1 Multiple Input Signature Register (MISR) (pronounced MYSER) 1. The multiple inputs are feed to the XOR gates before the flip-flop. 2. The property is similar to LFSR. type 2

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**MISR Matrix Equation di (t) – output response on POi at time t . 1**

. 1 X0 (t + 1) X1 (t + 1) . Xn-3 (t + 1) Xn-2 (t + 1) Xn-1 (t + 1) 1 . h1 … . 1 hn-2 . 1 hn-1 X0 (t) X1 (t) . Xn-3 (t) Xn-2 (t) Xn-1 (t) d0 (t) d1 (t) . dn-3 (t) dn-2 (t) dn-1 (t) = +

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**Modular MISR Example X0 (t + 1) X1 (t + 1) X2 (t + 1) 1 = X0 (t)**

1 = X0 (t) X1 (t) X2 (t) d0 (t) d1 (t) d2 (t) +

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**Multiple Signature Checking**

Use 2 different testing epochs: 1st with MISR with 1 polynomial 2nd with MISR with different polynomial Reduces probability of aliasing – Very unlikely that both polynomials will alias for the same fault Low hardware cost: A few XOR gates for the 2nd MISR polynomial A 2-1 MUX to select between two feedback polynomials

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Summary LFSR pattern generator and MISR response compacter – preferred BIST methods BIST has overheads: test controller, extra circuit delay, Input MUX, pattern generator, response compacter, DFT to initialize circuit & test the test hardware BIST benefits: At-speed testing for delay & stuck-at faults Drastic ATE cost reduction Field test capability Faster diagnosis during system test Less effort to design testing process Shorter test application times

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1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

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