Introduction to PCI System Architecture

Introduction to PCI System Architecture

Contents: Introduction to PCI System PCI Bus Arbitration
The PCI Commands The Read and Write Transfers Premature Transaction Termination Shared Resource Acquisition Error Detection and Handling Configuration Related Issues Interrupt Related Issues PCI Cache Supports Expansion ROMs sa

Introduction to PCI System

Direct-Connect Approach(VESA)
Main memory CPU Local Bus Cache Memory Bus Device Local Bus Expansion Bridge Local Bus Design Constraint: 1. Redesign is necessary for next generation processor. 2. Only one local device is permitted. 3. Design of local bus inter -face is difficult. 4. Transfer with one device is not permitted while the local bus is involved in a transfer with another device. Expansion Bus X-Bus Buffer Expansion Connectors X-Bus I/O Device I/O Device I/O Device

Buffered Approach(VESA)
CPU Local Bus Cache Memory Bus Expansion Bridge Bus Buffer Buffered Local Bus Expansion Bus X-Bus Buffer Device I/O Device I/O Device I/O X-Bus A maximum of three local bus devices can be placed on the buffered local bus. I/O Device I/O Device I/O Device

Workstation Approach(PCI)
Video Memory Main Memory CPU Memory Bus CPU Local Bus Host/PCI Cache/Bridge Audio Peripheral Motion Video Peripheral PCI Bus Expansion Bus Bridge Graphics Adapter SCSI Host Bus Adapter Adapter LAN LAN Advantage: 1. cpu-> L1,L2, Device-> Memory 2. cpu-> L1,L2, Device -> device (memory) 3. render interface independent of the processor bus Video Frame Buffer Disk SCSI BUS Expansion Bus Tape Bus Master Memory Slave I/O Slave ROM CD

Transfer Rate Comparison:
Bus Bus Frequency Transfer Transfer Rate ISA MHz 2 byte / 2 clock MB/s EISA MHz 4 byte / 1 clock MB/s ( Burst Mode) VESA 33 MHz 4 byte / 1 clock MB/s ( Read, Burst ) 4 byte / 2 clock MB/s ( Write, Burst ) PCI 33 MHz 4 byte / 1 clock MB/s 8 byte / 1 clock MB/s 66 MHz 4 byte / 1 clock MB/s 8 byte / 1 clock MB/s ( Burst Mode )

PCI: Peripheral Component Interconnect
Major PCI Revision 2.1 Features  Processor Independence  Support for up to 256 PCI functions per PCI bus  Low power consumption ( Draw as little current as possible )  Burst used for all read and write transfers  Supports 66 MHz operation, 64bit bus width  Fast access ( 60ns at bus speed 33 MHz )  Concurrent bus operation  Bus master support  Hidden bus arbitration  Low pin count ( Initiator:49pins, Target:47 pins )  Transaction integrity check( Parity check)  Three address spaces ( Memory, I/O, Configuration )  Auto configuration( Configuration register )  Software Transparency

PCI-Compliant Device Signals
For Slave only For Master only Required Signals Optional Signals AD[31:00] AD[63:32] Address/Data and Command 64-bit Extension C/BE[3:0]# PCI COMPLIANT DEVICE C/BE[7:4]# PAR PAR64 REQ64# FRAM# ACK64# TRDY# LOCK# Atomic Access Interface Control IRDY# INTA# STOP# INTB# DEVSEL# Interrupt Request INTC# IDSEL INTD# Error Reporting PERR# CLKRUN# Clock Control SERR# SBO# Snoop Result REQ# SDON Arbitration GNT# TDI TDO CLK TCK JTAG System RST# TMS TRST#

PCI Bus Arbitration

Initiator/ Target Initiator ( Master ): The device that initiates a transfer Target ( Slave ): The device that currently addressed by the initiator for the purpose of performing a data transfer PCI Arbiter GNT0# GNT1# GNT2# GNT3# REQ0# REQ1# REQ2# REQ3# PCI Device PCI Device PCI Device PCI Device MASTER Address, Command/ Data, Byte Enables/ Parity PCI Device Bridge DRAM SLAVE SLAVE SLAVE

PCI Bus Arbitration Algorithm
First Group Master X Master Y Master A Second Group Master B Master Z A B X A B Y A B Z A B X Fairness ( fixed, rotational ) Bus Parking( on specified master, on last master that acquired the bus ) Hidden Bus Arbitration( REQ#, GNT#) LT ( Latency Timer ): The minimum amount of time that the bus master is permitted to retain ownership of the bus 1.Fairness: higher priority master will not dominate bus to the exclusion of lower priority master 2. If the master has another burst to perform after current transaction, REQ# is asserted.

Example of PCI Bus Arbitration Between Two Masters
( Master B has higher priority than Master A) 1 2 3 4 5 6 7 8 9 10 11 12 CLK REQA# ( Master A -> Arbiter ) REQB# ( Master B -> Arbiter ) GNTA# ( Arbiter -> Master A ) GNTB# ( Arbiter -> Master B ) LT not expired FRAME# ( Master -> Target ) IRDY# ( Master -> Target ) TRDY# ( Target -> Master ) AD ADDRESS DATA DATA DATA ADDRESS DATA ADDRESS DATA ( Master <-> Target ) A B A

Arbitration for Fast Back-To-Back Accesses
1 2 3 4 5 6 7 8 CLK REQ#- GNT# FRAME# AD ADDRESS DATA ADDRESS DATA IRDY# TRDY# DEVSEL#

Delayed Transaction MTXC Master Target PIIX4 Delayed Transaction
Request Phase: Target latches the request and issues retry Completion Phase: Transaction completes on the target bus Target cannot respond within 16 clocks: MTXC Master 1. Address, Command, Byte Enables latched by PIIX4 2. Retry issued to MTXC ( Request Phase ) Target PIIX4 3. Requested data fetched in buffer ( Completion Phase ) 4. Master Retries the transaction with the same address, command, data ISA Device OR no Retry within 215 clocks Discard the data

Commands That can Use Delayed Transactions
Interrupt Acknowledge I/O Read I/O Write Memory Read Memory Read Line Memory Read Multiple Configuration Read Configuration Write

The PCI Commands

PCI Command Types C/BE#[3:0] is used to indicate the command or transaction type during the address phase C/BE[3::0]# Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate

PCI Interrupt Acknowledge Transaction
1 2 3 4 5 CLK FRAME # ( Host Bridge -> INT Controller ) AD Stable Pattern VECTOR ( Host Bridge < -> INT Controller ) C/BE # Byte Enables INT ACK CMD ( Host Bridge -> INT Controller ) IRDY # TRDY # DEVSEL # ( INT Controller-> Host Bridge ) GNT #

The Special Cycle Transaction( Halt / Shut Down)
Message Code Message Type ( on AD[15:0] 0000h Shut Down 0001h Halt 0002h x86-specific message 0003h-ffffh Reserved The Special Cycle Transaction( Halt / Shut Down) Terminated with Master Abort 1 2 3 4 5 6 7 8 CLK For an initiator to broad- cast a message to one or more targets. Message type on AD[15:0] Message-dependent data field on AD[31:16] Byte Enable on C/BE#[3:0] FRAME# AD[31:0] Stable Pattern Message C/BE#[3:0] Special Cmd Byte Enables IRDY# TRDY# DEVSEL# GNT# 7 clocks

The Read and Write Transfers

Read Transaction ( 33.33 Mb/s )
CLK 1 2 3 4 5 6 7 8 9 FRAME# Wait state for bus ownership AD ADDRESS DATA-1 DATA-2 DATA-3 C/BE# BUS CMD BYTE ENABLES BYTE ENABLES BYTE ENABLES IRDY# One more clock before initiator ready to receive data Avoid bus contention TRDY# Some time is needed for fetching data DEVSEL# ADDRESS PHASE DATA PHASE DATA PHASE DATA PHASE

Optimized Read Transaction
( 132 Mb/s) 1 2 3 4 5 6 7 8 Burst Transfer: 1. If target memory is cacheable. 2. If target memory is prefetchable CLK FRAME# AD Address Data1 Data2 Data3 C/BE# Byte Enables Byte Enables BUS CMD Byte Enables IRDY# TRDY# DEVSEL# GNT#

Write Transaction ( 44.44 Mb/s )
CLK 1 2 3 4 5 6 7 8 9 FRAME# AD ADDRESS DATA-1 DATA-2 DATA-3 C/BE# BUS CMD Byte EN Byte EN BYTE ENABLES IRDY# TRDY# DEVSEL#

Optimized Write Transaction
( 132 Mb/s) 1 2 3 4 5 6 7 8 CLK FRAME# AD Address Data1 Data2 Data3 C/BE# Byte Enables Byte Enables Byte Enables BUS CMD IRDY# TRDY# DEVSEL# GNT#

Addressing Addressing Sequence During Memory Burst
 Linear ( or Sequential ) address mode  Cache Line wrap mode AD1 AD0 Addressing Sequence Linear Reserved Cacheline wrap Reserved PCI I/O Addressing  AD[31:2] : Target DW of I/O space  AD[1:0] : The Least-significant byte within the DW that the initiator wishes to transfer with ( 00 = byte 0, 01 = byte 1 )

64 bit PCI Extension REQ64#, ACK64#, PAR64, AD[64::32], C/BE[7::4]

64-bit Read Request with 64-bit Transfer
CLK 1 2 3 4 5 6 7 8 9 FRAME# REQ64# AD[31::00] ADDRESS DATA-1 DATA-3 DATA-5 AD[63::32] DATA-2 DATA-4 DATA-6 C/BE[3::0]# BUS CMD BE# ‘s C/BE[7::4]# BE# ‘s IRDY# TRDY# DEVSEL# ACK64#

64-bit Write Request with 32-bit Transfer
CLK 1 2 3 4 5 6 7 8 9 FRAME# REQ64# AD[31::00] ADDRESS DATA-1 DATA-2 DATA-3 AD[63::32] DATA-2 C/BE[3::0]# BUS CMD BE# ‘s-1 BE# ‘s-2 BE# ‘s-3 C/BE[7::4]# BE# ‘s-2 IRDY# TRDY# DEVSEL# ACK64#

64-bit Dual Address Read Cycle
CLK 1 2 3 4 5 6 7 8 FRAME# AD[31::00] LO-ADDR HI-ADDR DATA-1 DATA-3 C/BE[3::0]# DUAL AD BUS CMD BE# [3::0] AD[63::32] HI-ADDR DATA-2 DATA-4 C/BE[7::4]# BUS CMD BE# [7::4] IRDY# TRDY# DEVSEL# REQ64# ACK64#

Premature Transaction Termination

Master Initiated Termination
Reasons Transaction completed normally ( Not premature transaction termination ) Initiator been preempted ( GNT# removed )  Preemption during timeslice by another bus master  Timeslice expiration followed by preemption Master abort  No target respond to the address ( DEVSEL# not asserted)  No device resides at the address  Special cycle  Configuration accessing a non-existent target

Internal LT time out sensed
Preemption Example 1 2 3 4 5 6 7 CLK Preempted GNT# FRAME# Internal LT time out sensed IRDY# TRDY# Timer Expiration Example CLK Preempted GNT# FRAME# Time out sensed IRDY# TRDY#

Example of Master-abort on Single-Data Phase Transaction
1 2 3 4 5 6 7 8 CLK FRAME# IRDY# TRDY# Fast Medium Slow Bridge DEVSEL# Master Abort : Target doesn’t claim transaction

Target Initiated Termination( STOP# )
Disconnect Reasons Target slow to complete a data phase which is neither the first nor the final data phase ( more than 8 PCI clocks ) Targets don’t support burst mode Memory target doesn’t understand address sequence Transfer cross over target’s address boundary Burst memory transfer crosses cache line boundary Retry ( if the target cannot permit any data to be transferred ) Reasons Target very slow to complete first data phase ( Greater than 16 PCI clocks ) Snoop hit on modified cache line Resource busy Memory target locked

Target Abort Reasons ( if the target detects fatal error )
Broken Target I/O addressing error Address phase parity error Master abort on other side of PCI-to-PCI bridge

Type A Disconnect Type B Disconnect
Know in advance that the next data transfer takes more than 8 PCI clock 1 2 3 4 1 2 3 4 CLK CLK FRAME# FRAME# IRDY# IRDY# TRDY# TRDY# STOP# STOP# DEVSEL# DEVSEL# Data Transfer Data Transfer TRDY# asserted, STOP# asserted, DEVSEL# asserted, IRDY# deasserted TRDY# asserted, STOP# asserted, DEVSEL# asserted, IRDY# asserted

without IRDY# Asserted TRDY# deasserted, STOP# asserted
Type C Disconnect with IRDY# Asserted Type C Disconnect without IRDY# Asserted Current data transfer takes more than 8 PCI clock 1 2 3 4 1 2 3 4 CLK CLK FRAME# FRAME# IRDY# IRDY# TRDY# TRDY# STOP# STOP# DEVSEL# DEVSEL# TRDY# deasserted, STOP# asserted DEVSEL# asserted Data Transfer Data Transfer

Without IRDY# Asserted
Retry Received With IRDY# Asserted Retry Received Without IRDY# Asserted 1 2 3 4 1 2 3 4 CLK CLK FRAME# FRAME# IRDY# IRDY# TRDY# TRDY# STOP# STOP# DEVSEL# DEVSEL# TRDY# deasserted, STOP# asserted DEVSEL# asserted No Data Transfer No Data Transfer Occurs in the first data phase

TRDY# deasserted, STOP# asserted
Target Abort Example 1 2 3 4 CLK FRAME# Master’s response to target abort: Generates an interrupt to alert is related device to check its status. Generates SERR# IRDY# TRDY# STOP# DEVSEL# TRDY# deasserted, STOP# asserted DEVSEL# deasserted

Shared Resource Acquisition

Shared Resource Acquisition
LOCK#  Usage : Perform read/modify/write of a memory semaphore as an atomic series to avoid Synchronization Problem.  Solutions: Bus LOCK : Permissible but not preferred Resource LOCK: Preferred

Starting an Exclusive Access
( Establishing LOCK#) 1 2 3 4 5 CLK FRAME# ( Master -> Target ) LOCK# ( Master -> Target ) AD ADDRESS DATA ( Master < -> Target ) IRDY# ( Master -> Target ) TRDY# ( Target -> Master ) DEVSEL# ( Target -> Master ) GNT# ( Arbiter -> Target ) LOCK# Mechanism Availability:  Do not assert REQ# if LOCK# is currently asserted.  If FRAME# and LOCK# are deasserted, assert its REQ#.  The master continue to monitor LOCK# while waiting for GNT#. If LOCK# is sampled asserted, the master deasserted its REQ#.  When the master samples bus idle ( FRAME# & IRDY# deasserted) and LOCK# deasserted, it has acquisition of the bus and of the LOCK#.

Accessing a Locked Agent : Retry
1 2 3 4 5 CLK FRAME# LOCK# (driven low by master holding lock) ADDRESS DATA AD IRDY# TRDY# STOP# DEVSEL# Retry GNT#

Continuing & Completing an Exclusive Access
1 2 3 4 5 CLK FRAME# Release LOCK# Continue ADDRESS DATA AD IRDY# TRDY# DEVSEL# GNT#

Error Detection and Handling
When Parity Error occurs: Configuration status register : DETECTED PARITY ERROR Configuration command register: PARITY ERROR RESPONSE Assert PERR# Devices excluded from PERR# Requirement Chipsets Devices that don’t deal with OS/Application program or data

Parity on Read Transaction
1 2 3 4 5 6 7 8 9 CLK FRAME# AD 1st Data 2nd Data Address 3rd Data C/BE# 1st Byte Enables 2nd Byte Enables 3rd Byte Enables BUS CMD PAR Add phase parity 1st Data parity 2nd Data parity 3rd Data Parity 3rd phase PERR# earliest latest PERR# 1st phase PERR# 2nd phase PERR# IRDY# TRDY# DEVSEL#

Parity on Write Transaction
1 2 3 4 5 6 7 8 9 CLK FRAME# AD 1st Data 2nd Data Address 3rd Data C/BE# 1st Byte Enables 2nd Byte Enables BUS CMD 3rd Byte Enables PAR Add phase parity 1st Data parity 2nd Data parity 3rd Data Parity 3rd phase PERR# earliest latest PERR# 1st phase PERR# 2nd phase PERR# IRDY# TRDY# DEVSEL#

Configuration Related Issues

Configuration Address Space Format
Byte Number 3 2 1 00 Double Word Number Configuration Header Space 15 16 Device Specific Configuration Registers 63

Configuration Registers Type 0 Configuration Space Header
31 16 15 Required configuration registers Device ID Vendor ID 00h Command Status 04h Class Code Revision ID 08h Latency Timer Cache Line Size BIST Header Type 0Ch 10h Base Address Registers 24h Cardbus CIS Pointer 28h 2Ch Subsystem ID Subsystem Vendor ID Expansion ROM Base Address 30h Reserved 34h Reserved 38h Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch

Command Register Bit Assignment
15 10 9 8 7 6 5 4 3 2 1 Reserved Fast Back-to-Back Enable SERR# Enable Wait Cycle Control Parity Error Response Palette Snoop Enable Memory Write and Invalidate Enable Special Cycle Monitoring Enable Mastering Memory Access Enable I/O Access Enable Status Register 15 14 13 12 11 10 9 8 7 6 5 4 Reserved 66MHz-Capable UDF Supported Fast Back-to-Back Enable Data Parity Reported DEVSEL Timing Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error

Class Code Register Header Type Register Class Code Sub-Class Code
23 16 15 8 7 o Class Code Sub-Class Code Prog I/F Device specific programming interface Basic function More specific device subclass Eg h h h Bridge device PCI/ISA bridge Header Type Register 7 6 Header Type Configuration Header Format 0 = single function device 1 = multi function device

Memory Base Address Register
BIST Register Reserved Completion Code Start BIST BIST Capable Memory Base Address Register 31 4 3 2 1 Base Address Prefetchable Type Memory space indicator Bits 2-1 Base register is 32 bits wide and can be mapped anywhere in the 32-bit memory space. Base register is 32 bits wide must be mapped below 1M in memory space. Base register is 64 bits wide and can be mapped anywhere in the 64-bit memory space. Reserved Bit 3 : set 1 if prefetchable, set 0 otherwise

Expansion ROM Base Address (Upper 21 bits)
I/O Base Address Register 31 2 1 Base Address 1 Reserved I/O space indicator Expansion ROM Register 31 11 10 1 Expansion ROM Base Address (Upper 21 bits) Reserved Address decode enable

Configuration Transactions
Usage: Access PCI configuration registers A PCI device or host/PCI bridge require 64 doubleword of config. register Each PCI function requires 64 doubleword of config. register Transaction type: 1. Type 0 configuration read or write transaction 2. Type 1 configuration read or write transaction 3. Memory mapped configuration mechanism ( PowerPC ) Configuration mechanism: 1. Mechanism 1 ( Preferred) 2. Mechanism 2

Peer Host/PCI Bridges Host Bus Bridge A Bridge B PCI Bus 0 PCI Bus 4
System Memory Processor Memory controller Host Bus Bridge A Bridge B PCI Bus 0 PCI Bus 4 Expansion Bridge Bridge D PCI Device Bridge E PCI Bus 0 PCI Device Bridge C PCI Bus 0 PCI bus 1 Expansion bus PCI bus 3 PCI bus5 Bridge C PCI bus 2

Type 0 Configuration Transaction
Two 32 bit I/O ports are utilized at I/O address: CONFIG_ADDRESS PORT: 0CF8 h CFB h CONFIG_DATA PORT : 0CFC h CFF h Configuration Address Register at 0CF8h Bus Number Device Number Function Number DW Number 1 = Enable Configuration space mapping Reserved 0CFBh 0CFAh 0CF9h 0CF8h Contents of the AD bus during address phase Function Number DW Number Reserved 0CFBh 0CFAh 0CF9h 0CF8h

Implementation of IDSEL
Bus Number Device Number Function Number DW Number Reserved Decoder Device Number ……… …….. …….. Function Number DW Number IDSEL PCI Slot 1 IDSEL PCI Slot 4 IDSEL PCI Slot 3 IDSEL PCI Slot 2 ....

Type 0 Configuration Read Access
1 2 3 4 5 6 7 8 9 CLK FRAME# AD Address Data C/BE# Config Read CMD Byte Enables IRDY# TRDY# IDSEL# GNT#

Configuration Mechanism 1 START
Pass PCI-to-PCI bridge Processor write to config. address reg. at I/O port 0CF8 Target bus in the range Host/PCI bridge YES Bus num the same YES Bus num the same NO NO Type 0 configuration read or write at config. data port 0CFC Type 0 configuration read or write at config. data port 0CFC Type 1 config. transaction Type 1 config. transaction

Interrupt Related Issues

Value to be Hardwired into Interrupt Pin Register
Interrupt Signal Bonded To Value Hardwired In Pin Register Device doesn’t generate interrupts 00h INTA# pin 01h INTB# pin 02h INTC# pin 03h INTD# pin 04h Interrupt Line Register Values System IRQ Line Interrupt Routed to Value to be Written In Line Register IRQ0 0d IRQ1 1d IRQ2 2d IRQ d

Interrupt Design Programmable Interrupt router INTA# INTB# INTC# INTD#
Slave 8259 INTA# INTB# INTC# INTD# INTA# IRQ8-15 INTA# INTB# INTC# INTD# Master 8259 INTA# INTA#INTB# IRQ0-7 INTA#

Interrupt Chaining Device 8259 If INT A and INT B both routed to IRQ1:
Entry 1 ISR 1 IRQ 1 INT A INT B IRQ 2 Entry 2 ISR 2 If INT A and INT B both routed to IRQ1: ISR 2 with Entry 1 embedded INT B IRQ 1 Entry 2

PCI Cache Support

SBO# : snoop backoff. ( HITM when assert.)
SDONE : snoop done SBO# : snoop backoff. ( HITM when assert.) The non-cacheable transaction is regardless of SDONE and SBO#. Write Through : only use SDONE Memory Target Interpretation of Snoop Result Signal from Bridge SDONE SBO# Description X Standby Clean snoop Hit on a modified line

Wait States Inserted Until Snoop Completes
CLK 1 2 3 4 5 6 FRAME# AD ADDRESS DATA IRDY# TRDY# SDONE SBO#

Hit to a Modified Line Followed by the Writeback
CLK 1 2 3 4 5 6 A B C FRAME# writeback transaction AD ADDRESS DATA-1 ADDRESS DATA-1 DATA-2 IRDY# TRDY# DEVSEL# STOP# SDONE SBO# STANDBY HITM HITM HITM HITM CLEAN STANDBY

Expansion ROMs

Purpose: ROM Detection: device-specific power-on self-test code
device-specific initialization code device-specific interrupt routine device-specific BIOS routine device-specific code to be executed during the system boot process ROM Detection: Check if Expansion ROM base address register exist Read if the first two locations on base address register contain 55AAh yes yes ROM exist Code image copied to system DRAM Execute initialization code

(Can be discarded after execution)
Code Image Format Header Data structure Runtime Module within the Image Runtime Code Initialization Code (Can be discarded after execution) Checksum Unused space PCI Expansion ROM Header Format Offset Length Value Description 0h h h ROM Signature,byte 1 1h h AAh ROM Signature,byte 2 2h-17h h XX Reserved(processor architecture unique data) 18h-19h h XX Pointer to PCI Data Structure

Unique Data Area in ROM Header
Offset Length Description 02h Overall size of the image 03h-05h Entry point for the initialization code ( POST performs a far call to initialize the device) 06h-17h Reserved

PCI Data Structure Format
Offset Length Description 0 h Signature, the string “PCIR” 4 h Vendor Identification 6 h Device Identification 8 h Pointer to Vital Product Data Ah PCI Data Structure Length Ch PCI Data Structure Revision Dh Class Code 10h Image Length 12h Revision Level of Code/Data 14h Code Type 15h Indicator (Bit 7, “1” last image) 16h Reserved

Introduction to PCI System Architecture

Similar presentations

Presentation on theme: "Introduction to PCI System Architecture"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

Introduction to PCI System Architecture

Similar presentations

Presentation on theme: "Introduction to PCI System Architecture"— Presentation transcript:

Similar presentations

About project

Feedback