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Introduction to PCI System Architecture. Contents: Introduction to PCI System PCI Bus Arbitration The PCI Commands The Read and Write Transfers Premature.

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Presentation on theme: "Introduction to PCI System Architecture. Contents: Introduction to PCI System PCI Bus Arbitration The PCI Commands The Read and Write Transfers Premature."— Presentation transcript:

1 Introduction to PCI System Architecture

2 Contents: Introduction to PCI System PCI Bus Arbitration The PCI Commands The Read and Write Transfers Premature Transaction Termination Shared Resource Acquisition Error Detection and Handling Configuration Related Issues Interrupt Related Issues PCI Cache Supports Expansion ROMs

3 Introduction to PCI System

4 Direct-Connect Approach(VESA) CPU Cache Main memory Local Bus Memory Bus Expansion Bridge Expansion Connectors X-Bus Buffer I/O Device Local Bus Design Constraint: 1. Redesign is necessary for next generation processor. 2. Only one local device is permitted. 3. Design of local bus inter -face is difficult. 4. Transfer with one device is not permitted while the local bus is involved in a transfer with another device. Expansion Bus X- Bus Local Bus Device

5 CPU Cache Local Bus Memory Bus Expansion Bridge X-Bus Buffer I/O Device Expansion Bus X- Bus Bus Buffer I/O Device I/O Device I/O Device I/O Device Buffered Approach(VESA) Buffered Local Bus A maximum of three local bus devices can be placed on the buffered local bus.

6 CPU Host/PCI Cache/ Bridge Workstation Approach(PCI) Memory Bus CPU Local Bus Main Memory Video Memory Audio Peripheral Motion Video Peripheral SCSI Host Bus Adapter SCSI BUS Disk Tape CD ROM Expansion Bus Video Frame Buffer Graphics Adapter Expansion Bus Bridge LAN Adapter PCI Bus Bus Master I/O Slave Memory Slave LAN

7 Transfer Rate Comparison: BusBus FrequencyTransfer Transfer Rate ISA8.33 MHz2 byte / 2 clock 8.33 MB/s EISA8.33 MHz4 byte / 1 clock 33 MB/s ( Burst Mode) VESA33 MHz4 byte / 1 clock 132 MB/s ( Read, Burst ) 4 byte / 2 clock 66 MB/s ( Write, Burst ) PCI33 MHz4 byte / 1 clock 132 MB/s 8 byte / 1 clock 264 MB/s 66 MHz4 byte / 1 clock 264 MB/s 8 byte / 1 clock 528 MB/s ( Burst Mode )

8 PCI: Peripheral Component Interconnect Major PCI Revision 2.1 Features Processor Independence Support for up to 256 PCI functions per PCI bus Low power consumption ( Draw as little current as possible ) Burst used for all read and write transfers Supports 66 MHz operation, 64bit bus width Fast access ( 60ns at bus speed 33 MHz ) Concurrent bus operation Bus master support Hidden bus arbitration Low pin count ( Initiator:49pins, Target:47 pins ) Transaction integrity check( Parity check) Three address spaces ( Memory, I/O, Configuration ) Auto configuration( Configuration register ) Software Transparency

9 AD[31:00]AD[63:32] C/BE[3:0]#C/BE[7:4]# PAR FRAM# TRDY# IRDY# STOP# DEVSEL# IDSEL SERR# REQ# GNT# CLK RST# PAR64 REQ64# ACK64# LOCK# INTA# INTB# INTC# INTD# TDI PCI COMPLIANT DEVICE PERR# PCI-Compliant Device Signals TDO TCK TMS TRST# CLKRUN# Address/Data and Command Interface Control Error Reporting Arbitration System Required SignalsOptional Signals 64-bit Extension Atomic Access Interrupt Request Clock Control SDON Snoop Result JTAG For Slave only For Master only SBO#

10 PCI Bus Arbitration

11 Initiator/ Target Initiator ( Master ): The device that initiates a transfer Target ( Slave ): The device that currently addressed by the initiator for the purpose of performing a data transfer PCI Device PCI Arbiter REQ0#REQ1#REQ2#REQ3# GNT0# GNT1#GNT2#GNT3# PCI Device MASTER SLAVE Address, Command/ Data, Byte Enables/ Parity DRAM SLAVE Bridge SLAVE

12 PCI Bus Arbitration Algorithm First Group Second Group Master A Master B Master X Master Y Master Z A B X A B Y A B Z A B X Fairness ( fixed, rotational ) Bus Parking( on specified master, on last master that acquired the bus ) Hidden Bus Arbitration( REQ#, GNT#) LT ( Latency Timer ): The minimum amount of time that the bus master is permitted to retain ownership of the bus

13 AD REQA# REQB# GNTA# GNTB# FRAME# ( Master B has higher priority than Master A) IRDY# TRDY# Example of PCI Bus Arbitration Between Two Masters 1234568 ADDRESS DATA 91011127 DATA ADDRESS DATA ADDRESS A BA ( Master A -> Arbiter ) ( Master B -> Arbiter ) ( Arbiter -> Master A ) ( Arbiter -> Master B ) ( Master -> Target ) ( Target -> Master ) ( Master -> Target ) ( Master Target ) CLK LT not expired

14 REQ#- GNT# DEVSEL# FRAME# 12345687 CLK IRDY# TRDY# AD ADDRESS DATAADDRESS DATA Arbitration for Fast Back-To-Back Accesses

15 Delayed Transaction Request Phase: Completion Phase: Target latches the request and issues retry Transaction completes on the target bus Master PIIX4 ISA Device 1. Address, Command, Byte Enables latched by PIIX4 2. Retry issued to MTXC ( Request Phase ) 3. Requested data fetched in buffer ( Completion Phase ) Target MTXC 4. Master Retries the transaction with the same address, command, data OR no Retry within 2 15 clocks Discard the data Target cannot respond within 16 clocks:

16 Commands That can Use Delayed Transactions Interrupt Acknowledge I/O Read I/O Write Memory Read Memory Read Line Memory Read Multiple Configuration Read Configuration Write

17 The PCI Commands

18 C/BE[3::0]# Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011I/O Write 0100Reserved 0101Reserved 0110Memory Read 0111Memory Write 1000Reserved 1001Reserved 1010Configuration Read 1011Configuration Write 1100Memory Read Multiple 1101Dual Address Cycle 1110Memory Read Line 1111 Memory Write and Invalidate PCI Command Types C/BE#[3:0] is used to indicate the command or transaction type during the address phase

19 VECTOR INT ACK CMD Byte Enables CLK FRAME # AD C/BE # IRDY # TRDY # 12345 DEVSEL # GNT # PCI Interrupt Acknowledge Transaction Stable Pattern ( Host Bridge -> INT Controller ) ( Host Bridge INT Controller ) ( Host Bridge -> INT Controller ) ( INT Controller-> Host Bridge )

20 GNT# DEVSEL# FRAME# CLK IRDY# TRDY# AD[31:0] 12345687 Stable Pattern Message C/BE#[3:0] Special Cmd Byte Enables The Special Cycle Transaction( Halt / Shut Down) Terminated with Master Abort For an initiator to broad- cast a message to one or more targets. Message type on AD[15:0] Message-dependent data field on AD[31:16] Byte Enable on C/BE#[3:0] 7 clocks Message Code Message Type ( on AD[15:0] 0000h Shut Down 0001h Halt 0002h x86-specific message 0003h-ffffh Reserved

21 The Read and Write Transfers

22 Read Transaction ( 33.33 Mb/s ) CLK 123456789 FRAME# AD C/BE# IRDY# TRDY# DEVSEL# ADDRESSDATA-1DATA-2DATA-3 BUS CMD ADDRESS PHASE DATA PHASE DATA PHASE DATA PHASE BYTE ENABLES Wait state for bus ownership One more clock before initiator ready to receive data Some time is needed for fetching data Avoid bus contention

23 GNT# DEVSEL# FRAME# CLK IRDY# TRDY# AD 12345687 AddressData1 C/BE# BUS CMD Byte Enables Data2Data3 Byte Enables Byte Enables Optimized Read Transaction ( 132 Mb/s) Burst Transfer: 1. If target memory is cacheable. 2. If target memory is prefetchable

24 CLK 123456789 FRAME# AD C/BE# IRDY# TRDY# DEVSEL# ADDRESSDATA-1DATA-2DATA-3 BUS CMD BYTE ENABLES Byte EN Write Transaction ( 44.44 Mb/s )

25 GNT# DEVSEL# FRAME# CLK IRDY# TRDY# AD 12345687 AddressData1 C/BE# BUS CMD Data2Data3 Byte Enables Byte Enables Optimized Write Transaction ( 132 Mb/s) Byte Enables

26 Addressing Addressing Sequence During Memory Burst Linear ( or Sequential ) address mode Cache Line wrap mode AD1AD0Addressing Sequence 0 0 Linear 0 1 Reserved 1 0 Cacheline wrap 1 1 Reserved PCI I/O Addressing AD[31:2] : Target DW of I/O space AD[1:0] : The Least-significant byte within the DW that the initiator wishes to transfer with ( 00 = byte 0, 01 = byte 1 )

27 64 bit PCI Extension REQ64#, ACK64#, PAR64, AD[64::32], C/BE[7::4]

28 123456789 ADDRESS DATA-1 DATA-3 DATA-5 DATA-2 DATA-4 DATA-6 BUS CMD BE# s CLK FRAME# REQ64# AD[31::00] AD[63::32] C/BE[3::0]# C/BE[7::4]# IRDY# TRDY# DEVSEL# ACK64# 64-bit Read Request with 64-bit Transfer

29 64-bit Write Request with 32-bit Transfer 123456789 ADDRESS DATA-1 DATA-3 DATA-2 BUS CMD BE# s-1 CLK FRAME# REQ64# AD[31::00] AD[63::32] C/BE[3::0]# C/BE[7::4]# IRDY# TRDY# DEVSEL# ACK64# DATA-2 BE# s-2 BE# s-3 BE# s-2

30 64-bit Dual Address Read Cycle 12345678 DUAL AD BE# [3::0] CLK FRAME# IRDY# TRDY# LO-ADDR HI-ADDR DATA-1 DATA-3 AD[31::00] C/BE[3::0]# BUS CMD AD[63::32] C/BE[7::4]# HI-ADDR DATA-2 DATA-4 BE# [7::4] BUS CMD DEVSEL# REQ64# ACK64#

31 Premature Transaction Termination

32 Master Initiated Termination Reasons Transaction completed normally ( Not premature transaction termination ) Initiator been preempted ( GNT# removed ) Preemption during timeslice by another bus master Timeslice expiration followed by preemption Master abort No target respond to the address ( DEVSEL# not asserted) No device resides at the address Special cycle Configuration accessing a non-existent target

33 GNT# FRAME# CLK IRDY# TRDY# 1234567 GNT# FRAME# CLK IRDY# TRDY# Preempted Internal LT time out sensed Preempted Time out sensed Preemption Example Timer Expiration Example

34 DEVSEL# FRAME# CLK IRDY# TRDY# 12345687 Example of Master-abort on Single-Data Phase Transaction FastMediumSlowBridge Master Abort : Target doesnt claim transaction

35 Target Initiated Termination( STOP# ) Disconnect Target Initiated Termination( STOP# ) Disconnect Target very slow to complete first data phase ( Greater than 16 PCI clocks ) Snoop hit on modified cache line Resource busy Memory target locked Reasons Target slow to complete a data phase which is neither the first nor the final data phase ( more than 8 PCI clocks ) Targets dont support burst mode Memory target doesnt understand address sequence Transfer cross over targets address boundary Burst memory transfer crosses cache line boundary Retry Reasons ( if the target cannot permit any data to be transferred )

36 Broken Target I/O addressing error Address phase parity error Master abort on other side of PCI-to-PCI bridge Target Abort Reasons ( if the target detects fatal error )

37 DEVSEL# FRAME# CLK IRDY# TRDY# 1234 Type A Disconnect STOP# Data Transfer DEVSEL# FRAME# CLK IRDY# TRDY# 1234 Type B Disconnect STOP# Data Transfer TRDY# asserted, STOP# asserted, DEVSEL# asserted, IRDY# deasserted TRDY# asserted, STOP# asserted, DEVSEL# asserted, IRDY# asserted Know in advance that the next data transfer takes more than 8 PCI clock

38 DEVSEL# FRAME# CLK IRDY# TRDY# 1234 Type C Disconnect with IRDY# Asserted STOP# Data Transfer DEVSEL# FRAME# CLK IRDY# TRDY# 1234 Type C Disconnect without IRDY# Asserted STOP# Data Transfer TRDY# deasserted, STOP# asserted DEVSEL# asserted Current data transfer takes more than 8 PCI clock

39 DEVSEL# FRAME# CLK IRDY# TRDY# 1234 Retry Received With IRDY# Asserted STOP# DEVSEL# FRAME# CLK IRDY# TRDY# 1234 Retry Received Without IRDY# Asserted STOP# No Data Transfer TRDY# deasserted, STOP# asserted DEVSEL# asserted Occurs in the first data phase

40 DEVSEL# FRAME# CLK IRDY# TRDY# 1234 Target Abort Example STOP# Masters response to target abort: Generates an interrupt to alert is related device to check its status. Generates SERR# TRDY# deasserted, STOP# asserted DEVSEL# deasserted

41 Shared Resource Acquisition

42 LOCK# Usage : Perform read/modify/write of a memory semaphore as an atomic series to avoid Synchronization Problem. Solutions: Bus LOCK : Permissible but not preferred Resource LOCK: Preferred

43 Starting an Exclusive Access ( Establishing LOCK#) 12345 CLK FRAME# LOCK# AD IRDY# TRDY# DEVSEL# ADDRESS DATA GNT# LOCK# Mechanism Availability: Do not assert REQ# if LOCK# is currently asserted. If FRAME# and LOCK# are deasserted, assert its REQ#. The master continue to monitor LOCK# while waiting for GNT#. If LOCK# is sampled asserted, the master deasserted its REQ#. When the master samples bus idle ( FRAME# & IRDY# deasserted) and LOCK# deasserted, it has acquisition of the bus and of the LOCK#. ( Master -> Target ) ( Master Target ) ( Master -> Target ) ( Target -> Master ) ( Arbiter -> Target )

44 Accessing a Locked Agent : Retry CLK FRAME# LOCK# AD IRDY# TRDY# STOP# ADDRESS DATA 12345 DEVSEL# (driven low by master holding lock) Retry GNT#

45 Continuing & Completing an Exclusive Access CLK FRAME# LOCK# AD IRDY# TRDY# DEVSEL# ADDRESS DATA 12345 Continue Release GNT#

46 When Parity Error occurs: Configuration status register : DETECTED PARITY ERROR Configuration command register: PARITY ERROR RESPONSE Assert PERR# Devices excluded from PERR# Requirement Chipsets Devices that dont deal with OS/Application program or data Error Detection and Handling

47 Parity on Read Transaction TRDY# DEVSEL# FRAME# CLK PAR PERR# AD 12345687 Address 1st Data C/BE# BUS CMD 3rd Data 2nd Byte Enables 3rd Byte Enables 1st Byte Enables 9 2nd Data IRDY# Add phase parity 1st Data parity 3rd Data Parity 2nd Data parity 1st phase PERR# 2nd phase PERR# 3rd phase PERR# earliest latest

48 Parity on Write Transaction TRDY# DEVSEL# FRAME# CLK PAR PERR# AD 12345687 Address 1st Data C/BE# BUS CMD 3rd Data 2nd Byte Enables 3rd Byte Enables 1st Byte Enables 9 2nd Data IRDY# Add phase parity 1st Data parity 3rd Data Parity 2nd Data parity 1st phase PERR# 2nd phase PERR# 3rd phase PERR# earliest latest

49 Configuration Related Issues

50 Configuration Address Space Format Configuration Header Space Device Specific Configuration Registers Byte Number Double Word Number 00 15 16 63 0123

51 Configuration Registers 00h 04h 08h 0Ch 10h 24h 28h 2Ch 30h 34h 38h 3Ch 0 151631 BIST Cache Line Size Base Address Registers Cardbus CIS Pointer Subsystem IDSubsystem Vendor ID Expansion ROM Base Address Reserved Max_LatMin_Gnt Interrupt PinInterrupt Line Type 0 Configuration Space Header Status Required configuration registers Latency Timer Device IDVendor ID Command Revision ID Class Code Header Type

52 Command Register Bit Assignment Reserved Fast Back-to-Back Enable DEVSEL Timing Data Parity Reported Signaled Target Abort Received Target Abort Received Master Abort 5067894 Status Register 53210 Reserved 678910 Fast Back-to-Back Enable SERR# Enable Wait Cycle Control Parity Error Response Palette Snoop Enable Memory Write and Invalidate Enable Special Cycle Monitoring Enable Mastering Memory Access Enable 4 I/O Access Enable 15 1413121110 66MHz-Capable UDF Supported Signaled System Error Detected Parity Error

53 Class Code Register Class CodeSub-Class CodeProg I/F o78151623 Basic functionMore specific device subclass Device specific programming interface Eg. 06h 01h 00h Bridge device PCI/ISA bridge Header Type Register 067 Header Type Configuration Header Format 0 = single function device 1 = multi function device

54 BIST Register Completion Code Reserved Start BIST BIST Capable 7 6 5 4 3 0 0 43210 Base Address 31 Prefetchable Type Memory space indicator Memory Base Address Register Bits 2-1 00 Base register is 32 bits wide and can be mapped anywhere in the 32-bit memory space. 01 Base register is 32 bits wide must be mapped below 1M in memory space. 10 Base register is 64 bits wide and can be mapped anywhere in the 64-bit memory space. 11 Reserved Bit 3 : set 1 if prefetchable, set 0 otherwise

55 Expansion ROM Base Address (Upper 21 bits)Reserved Expansion ROM Register 01101131 Address decode enable I/O Base Address Register 1 210 Base Address 31 Reserved I/O space indicator

56 Configuration Transactions Usage: Access PCI configuration registers A PCI device or host/PCI bridge require 64 doubleword of config. register Each PCI function requires 64 doubleword of config. register Transaction type: 1. Type 0 configuration read or write transaction 2. Type 1 configuration read or write transaction 3. Memory mapped configuration mechanism ( PowerPC ) Configuration mechanism: 1. Mechanism 1 ( Preferred) 2. Mechanism 2

57 Processor System Memory Bridge A Host Bus Expansion Bridge PCI Bus 0 Memory controller Bridge B Bridge DBridge EPCI Device PCI Bus 0 PCI DeviceBridge C PCI bus 1 PCI bus 3 PCI bus5 PCI bus 2 PCI Bus 4 Expansion bus PCI Bus 0 Peer Host/PCI Bridges

58 Type 0 Configuration Transaction CONFIG_ADDRESS PORT: 0CF8 h - 0CFB h CONFIG_DATA PORT : 0CFC h - 0CFF h Two 32 bit I/O ports are utilized at I/O address: 00 DW Number Function Number Device Number Bus Number Reserved 31 30 24 23 16 15 11 10 8 7 2 1 0 Configuration Address Register at 0CF8h 1 = Enable Configuration space mapping 0CF8h0CF9h0CFAh0CFBh Contents of the AD bus during address phase 00 DW Number Function Number Reserved 31 30 11 10 8 7 2 1 0 0CF8h0CF9h0CFAh0CFBh

59 00 DW Number Function Number Device Number Bus Number Reserved 31 30 24 23 16 15 11 10 8 7 2 1 0 00 DW Number Function Number 31 30 16 15 11 10 8 7 2 1 0 Implementation of IDSEL Decoder …….. Device Number 16 15 14 ………. 1 0 IDSEL PCI Slot 1 IDSEL PCI Slot 2 IDSEL PCI Slot 3 IDSEL PCI Slot 4....

60 TRDY# GNT# FRAME# CLK AD 12345687 Address C/BE# Byte Enables 9 IRDY# Config Read CMD IDSEL# Type 0 Configuration Read Access Data

61 Processor write to config. address reg. at I/O port 0CF8 Host/PCI bridge Bus num the same YES Type 0 configuration read or write at config. data port 0CFC NO Type 1 config. transaction START Pass PCI-to-PCI bridge Target bus in the range Bus num the same YES NO Type 0 configuration read or write at config. data port 0CFC Type 1 config. transaction Configuration Mechanism 1

62 Interrupt Related Issues

63 Interrupt Signal Bonded To Value Hardwired In Pin Register Device doesnt generate interrupts00h INTA# pin01h INTB# pin02h INTC# pin03h INTD# pin 04h System IRQ Line Interrupt Routed to Value to be Written In Line Register IRQ00d IRQ11d IRQ22d IRQ1515d Value to be Hardwired into Interrupt Pin Register Interrupt Line Register Values

64 INTA# INTA# INTB# INTA# INTB# INTC# INTD# INTA# INTA# INTB# INTA# INTB# INTC# INTD# IRQ8-15 Slave 8259 Master 8259 IRQ0-7 Programmable Interrupt router Interrupt Design

65 Interrupt Chaining Entry 1ISR 1 Entry 2ISR 2 INT B Entry 2 ISR 2 with Entry 1 embedded IRQ 1 Device8259 INT A INT B IRQ 1 IRQ 2 If INT A and INT B both routed to IRQ1:

66 PCI Cache Support

67 Snoop SDONE : snoop done SBO# : snoop backoff. ( HITM when assert.) The non-cacheable transaction is regardless of SDONE and SBO#. Write Through : only use SDONE Memory Target Interpretation of Snoop Result Signal from Bridge SDONE SBO# Description 0 X Standby 1 1 Clean snoop 1 0 Hit on a modified line

68 Wait States Inserted Until Snoop Completes CLK 123456 FRAME# AD SBO# IRDY# TRDY# SDONE ADDRESSDATA

69 Hit to a Modified Line Followed by the Writeback CLK 123456 FRAME# AD SBO# IRDY# TRDY# SDONE ADDRESSDATA-1 BCA ADDRESSDATA-1DATA-2 STOP# writeback transaction HITM CLEAN HITM STANDBY DEVSEL#

70 Expansion ROMs

71 Purpose: device-specific power-on self-test code device-specific initialization code device-specific interrupt routine device-specific BIOS routine device-specific code to be executed during the system boot process ROM Detection: Check if Expansion ROM base address register exist yes Read if the first two locations on base address register contain 55AAh yes ROM exist Code image copied to system DRAM Execute initialization code

72 Code Image Format PCI Expansion ROM Header Format Offset Length Value Description 0h 1h 55h ROM Signature,byte 1 1h 1h AAh ROM Signature,byte 2 2h-17h 16h XX Reserved(processor architecture unique data) 18h-19h 2h XX Pointer to PCI Data Structure Header Data structure Runtime Code Initialization Code (Can be discarded after execution) Checksum Unused space Runtime Module within the Image

73 Unique Data Area in ROM Header Offset Length Description 02h 1 Overall size of the image 03h-05h 3 Entry point for the initialization code ( POST performs a far call to initialize the device) 06h-17h 18 Reserved

74 Offset Length Description 0 h 4 Signature, the string PCIR 4 h 2 Vendor Identification 6 h 2 Device Identification 8 h 2 Pointer to Vital Product Data Ah 2 PCI Data Structure Length Ch 1 PCI Data Structure Revision Dh 3 Class Code 10h 2 Image Length 12h 2 Revision Level of Code/Data 14h 1 Code Type 15h 1 Indicator (Bit 7, 1 last image) 16h 2 Reserved PCI Data Structure Format


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