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P IPELINED A RCHITECTURE Prof.P.C.Patil Department of Computer Engg Matoshri College of Engg.Nasik M ICROPROCESSOR A RCHITECTURE UOP.

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Presentation on theme: "P IPELINED A RCHITECTURE Prof.P.C.Patil Department of Computer Engg Matoshri College of Engg.Nasik M ICROPROCESSOR A RCHITECTURE UOP."— Presentation transcript:

1 P IPELINED A RCHITECTURE Prof.P.C.Patil Department of Computer Engg Matoshri College of Engg.Nasik M ICROPROCESSOR A RCHITECTURE UOP S.E.C OMP (S EM -I)

2 Bus Cycles of

3 The internal and external bus operations of are synchronized by the clock signal. The perform variety of machine (bus) cycles in response to intemal requirements and external requirements There are seven types of machine (bus) cycles In each machine cycles corresponding status signals are activated. The memory read and memory write machine cycles can be locked to prevent another bus master from using the bus. Bus Cycles of

4 In each machine cycles corresponding status signals are activated. The memory read and memory write machine cycles can be locked to prevent another bus master from using the bus. Bus Cycles of

5 Seven types of machine (bus) cycles/operations. 1) Memory read 2) Memory write 3) I/O read 4) I/O write 5) Lestruction fetch 6) Interrupt acknowledge 7) Halt/Shut down Bus Cycles of

6 6

7 System Clock 7

8 System clock syrchronizes the internal and external bus operations in the 80386DX. The 80386DX can operate on four different clock speeds DX - 16 (16 MHz) DX - 20 (20 MHz) DX - 25 (2s MHz) DX- 33 (33 MHz) Operating frequency of the 80386DX is half of, the CLK2 frequency. Therefore, CLK2 of an 80386DX - 20 is driven by 40 MHz signal. (Shown in Fig below) System Clock 8

9 9

10 Bus States 10

11 Each machine (bus) cycle consists of at least two bus states T1 and T2, and each bus state consists of two CLK cycles. address and bus status 1. During the first bus state (T1), address and bus status pin are active. actual data lransfer 2. During the second bus state (T2), actual data lransfer takes place. The DX can perform two types of machine cycles : 1. Nonpipelined 2. Pipelined 2. Pipelined. Bus States 11

12 Dynamic Bus Sizing 12

13 Dynamic data bus sizing is a feature allowing direct processor connection to 32-bit or 16-bit data buses for memory or I/O. A single processor may connect to both size buses Transfers to or from 32 to 16 bit ports are supported by dynamically determining the bus width during each machine cycle. [Bar/Complement]) ) The 80386DX microprocessor's bus size 16 (BS-16 [Bar/Complement]) ) input is used to inform the 803B6DX at the currently addressed device is a 16-bit device rather than a 32-bit device Dynamic Bus Sizing 13

14 Nonpipelined Machine (Bus) Cycles 14

15 15 Nonpipelined Bus Cycle

16 During T1, the 803B6DX sends the address, bus status signal and control signals. In case of write cycle, data to be output is also send on the data bus, during T1. After address access time, read or write data transfer takes place over the data bus. This activity is carried out in T2. Nonpipelined Bus Cycle 16

17 Pipelined Machine (Bus) Cycles 17

18 Pipelining allows machine cycles to be overlapped. The main advantage of pipelining is that it increases the amount of time required for the memory or I/O device to respond. This time is also referred as access time. The 80386DX implements pipelining by overlapping addressing of the next bus cycle with the data transfer of previous bus cycle. 18 Pipelined Bus Cycle

19 19 Pipelined Bus Cycle

20 Fig shows that address becomes valid in T2 state of the previous bus cycle, and the data transfer for address takes place in T2-state of the current bus cycle. IMP :A n + 1 A n + 1 IMP : address A n + 1 becomes valid during T2 of the current bus cycle and actual data transfer for address A n + 1 takes place in T2 state of the next bus cycle. If the processor is 80386DX-20 then one T-state time is 50 ns. In pipelined bus cycle the access time for memory and I/O device is 100 ns whereas access time for memory and l/O device in nonpipelined bus cycle is approximately 50 ns. In pipelined bus cycle the access time for memory and I/O device is 100 ns whereas access time for memory and l/O device in nonpipelined bus cycle is approximately 50 ns. 20 Pipelined Bus Cycle

21 Nonpipelined Read Cycle 21

22 Enlarge Image

23 The sequence of events for the nonpipelined read cycle: starts at the beginning of phase in the T1 state 1. The read operation starts at the beginning of phase in the T1 state of the bus cycle. sends the address on the address bus enables signals(BE0 (Bar) - BE3 (Bar) ) 2. In this phase, 80386DX sends the address on the address bus and enables signals(BE0 (Bar) - BE3 (Bar) ) according to data transfer type. it activates ADS (Bar) indicate valid address 3. In the same phase, it activates ADS (Bar) signal to indicate valid address is placed on the address bus. phase 1T1 - state M/IO, D/C and W/R 4. In phase 1 of T1 - state it also activates the bus cycle definition signals : M/IO, D/C and W/R. Nonpipelined Read Cycle 23

24 beginning of phase 1 of T2 state activates BS16 (BAR) 5. At the beginning of phase 1 of T2 state, extemal device activates BS16 (BAR) signal. middle of phase 1 of T2-state. 6. Then samples this signal in the middle of phase 1 of T2-state. BS16 (BAR) =1 32-bit data transfer: If BS16 (BAR) =1 BS16 (BAR) =0 16-bit data transfer: If BS16 (BAR) =0 phase 2 of T2-state. 7. The DX does this data transfer in phase 2 of T2-state. end of phase 2 of T2-state READY (BAR) 8. At the end of phase 2 of T2-state the READY (BAR) signal is sampled. logic 1wait state 9. The logic 1 on this signal inserts wait state in the current bus cycle to extend the bus cycle. 24 Nonpipelined Read Cycle

25 LOCK (Bar) low 10. The LOCK (Bar) signal low indicates that it is bus locked cycle. 11. If bus cycles are locked the other bus master is not allowed to take control of the bus between two locked bus cycles. 25 Nonpipelined Read Cycle

26 Nonpipelined Write Cycle 26

27

28 The sequence of events for the nonpipelined read cycle: 1. It is similar to nonpipelined read cycle. write operation beginning of phase 1 in the T1 state 2. The write operation starts at the beginning of phase 1 in the T1 state of the bus cycle. address on the address busBE0 (Bar) -BE3 (Bar) 3. In this phase, 80386DX sends the address on the address bus and enables signals BE0 (Bar) -BE3 (Bar) according to data transfer type. ADS (Bar) 4. After sending address in the same phase it activates its ADS (Bar) signal to indicate valid address is placed on the address bus. Nonpipelined Write Cycle 28

29 10. In phase 1 of T1-state M/IO, D/C and W/R 10. In phase 1 of T1-state it also activates the bus cycle definition signals M/IO, D/C and W/R beginning of phase 2 of T1-state valid until the start of phase 2 of the T1-state 11. At the beginning of phase 2 of T1-state, it sends data on the data bus. This data remains valid until the start of phase 2 of the T1-state of the next bus cycle. end of phase 2 of T1- state, ADS (Bar) inactive logic At the end of phase 2 of T1- state, ADS (Bar) is returned to its inactive logic 1 states. 13. The address bus, byte enable pins, and bus status pins remain active through the end of the write cycle 13. The address bus, byte enable pins, and bus status pins remain active through the end of the write cycle. 29 Nonpipelined Write Cycle

30 (Bar) 10. In the middle of phase 1 of T2-State, 80386DX samples BS16 (Bar) input. 11. If this signal is high, DX does the 32-bit data transfer otherwise 80386DX performs 16-bit data transfer. 30 Nonpipelined Write Cycle Comparison of Read and Write Cycle

31 Pipelined Read/Write Cycle 31

32

33 address for the next bus cycle is sent during the T2 - state In the pipelined bus cycle the address for the next bus cycle is sent during the T2 - state of the current cycle. NA (next address) NA (next address) signal initiates address pipelining. Pipelined Read/Write Cycle 33

34 beginning of phase 2 of any TADS It then samples NA signal at the beginning of phase 2 of any T state in which ADS is not active, specifically. second T-state In the second T-state of a non-pipelined address cycle first T-state pipelined In the first T-state of a pipelined address cycle any wait state non-pipelined In any wait state of a non-pipelined address or pipelined address cycle unless NA has already been sampled active 34 Pipelined Read/Write Cycle

35 NA (Bar) T2 of cycle 2 execute next cycle as pipelined The NA (Bar) is tested as 0 (active) during T2 of cycle 2 which ensures that 80386DX has to execute next cycle as pipelined bus cycle. The cycle 2 (nonpipelined read cycle) is also extended with one wait state because READY pin is not active, wait state in wait state, the valid address for the next bus cycle is sent on the address bus as next bus cycle is pipelined bus cycle. 35 Pipelined Read/Write Cycle

36 next cycle (cycle 3) pipelined write The next cycle (cycle 3) is pipelined write cycle. phase 2 of T1p-state In this, data is sent on the data bus in phase 2 of T1p-state and remains valid for the rest of the cycle. The READY signal is sampled at the end of T2p - state. low, As it is low, write cycle is completed without wait state. 36 Pipelined Read/Write Cycle

37 next cycle (cycle 4) pipelined read cycle. The next cycle (cycle 4) is pipelined read cycle. In this, READY signal is tested 0 at the end of phase 2 of T2p - state. This means that read cycle is completed without wait state. due to pipelined address cycle, access time is extended and one state (T-wait) of read cycle is saved. It is important to note that due to pipelined address cycle, access time is extended and one state (T-wait) of read cycle is saved. 37 Pipelined Read/Write Cycle


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