The block diagram shows a typical PCI Local Bus system architecture. In this example, the processor/cache/memory subsystem is connected to PCI through a PCI bridge. This bridge provides a low latency path through which the processor may directly access PCI devices mapped anywhere in the memory or I/O address spaces. Typical PCI Local Bus implementations will support up to four add-in board connectors, although expansion capability is not required. To provide a quick and easy transition from 5V to 3.3V component technology, PCI defines two add-in board connectors: one for the 5V signaling environment and one for the 3.3V signaling environment. A 5 volt board which plugs into only the 5V connector, a universalboard which plugs into both 5V and 3.3V connectors, and a 3.3V volt board which plugs into only the 3.3V connector. PCI Local Bus Overview
Data Transfer Rate of Clock Frequency and Bus Width
PCI-X Features The PCI-X bus is a higher frequency, higher performance, higher efficiency bus compared to the PCI bus. PCI-X supports 8-10 loads or 4 connectors at 66MHz and 3-4 loads or 1-2 connectors at 133MHz. The peak bandwidth achievable with 64-bit 133MHz PCI-X is 1064MBytes/sec. Following the first data phase, the PCI-X bus does not allow wait status during subsequent data phases. Most PCI-X bus cycles are burst cycles and data generally transferred in blocks of no less than 128 Bytes. This results in higher bus unitization. Further, the transfer size is specified in the attribute phase of PCI-X transactions. This allows for more efficient device buffer management. The
PCI to PCI Bridge The PCI Specification theoretically supports 32 devices per PCI bus. This means that PCI enumeration software will detect and recognize up to 32 devices per bus. However, as a rule of thumb, a PCI bus can support a maximum of 10-12 electrical loads (devices) at 33MHz. Connectors on the PCI bus are counted as 2 loads because the connector is accounted for as one load and the peripheral card with a PCI device is the second load. To connect any more than 10-12 loads in a system requires the implementation of a PCI to PCI bridge. The PCI specification theoretically supports up to 256 buses in a system. This means that PCI enumeration software will detect and recognize up to 256 PCI bridges per system.
Device or Load #1 Device or Load #2 PCI, PCI-X Bus PCI Slots PCI Bridge Secondary PCI Bus Device or Load x Device or Load y A PCI-to-PCI Bridge allows a system to add more loads to the bus by creating a separate secondary bus More Devices or Loads on Motherboard More Slots for Adapter Cards Multiple Devices on Card Needing Access to PCI/PCI-X Bus Device A Device B PCI Bridge Device C Benefits on PCI to PCI Bridge
66MHz Device 33MHz Device Bus Segment downshifted to 33 MHz 66MHz Device PCI Bridge 33MHz Device 33MHz Bus Segment running at full 66 MHz PCI Bridges may also be used for isolation A PCI bus segment will always downshift to the lowest speed device residing on the bus. A PCI Bridge can be used to isolate the slower device so that it doesnt slow down the other faster devices Benefits on PCI to PCI Bridge (Continued)
Asynchronous Mode Allows the secondary bus to run at a frequency asynchronous from the primary Synchronous bridges limit the secondary bus frequency to either the same frequency or half the frequency of the primary bus Secondary bus frequency may run faster than the primary bus frequency Interface/upgrade for slower legacy products PI7C815xB PCI Bridge Legacy device 25 MHz 33 MHz 66 MHz 50 MHz System Primary Bus PI7C815xB PCI Bridge 66MHz device 33 MHz 66 MHz System Primary Bus Legacy 33MHz device Benefits on PCI to PCI Bridge (Continued)
PCI Bridge Applications Routers & Switches - #1 Application HBA and NIC Cards - #2 Application Fibre Channel Adapter Cards-Servers GbE NIC cards-Servers RAID Controller Cards PC Add in Cards – #3 Application Graphics Cards Video Encoder/Decoder Cards Industrial PC Video Surveillance Multi Function Printers And Many More!