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JAZiO Incorporated 1 JAZiO JAZiO Incorporated Digital Signal Switching Technology.

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Presentation on theme: "JAZiO Incorporated 1 JAZiO JAZiO Incorporated Digital Signal Switching Technology."— Presentation transcript:


2 JAZiO Incorporated 1 JAZiO JAZiO Incorporated Digital Signal Switching Technology

3 JAZiO Incorporated 2 What is JAZiO Technology? A new method of interchip I/O switching –At high data rate with low latency –With low power –At low cost Effectiveness is due to using –Differential sensing with a single pin per bit –Built in timing Based on looking for change-of-data first

4 JAZiO Incorporated 3 Traditional Signal Driving All information is transmitted during t RF (1/3 of bit time) The rest of the bit time is just wasted! One bit time Next bit time t RF t SU t HD Sharp Edges Cause: Ground Bounce! Cross Talk! Ringing! EMI! High Power!

5 JAZiO Incorporated 4 Pseudo Differential Signal Sensing Sensing level about 1/3 of switching level The rest of the switching level is just wasted! Large switching levels cause: Ground Bounce! Cross Talk! Ringing! High Power! One bit time Next bit time Sensing Level V REF Switching Level 0.8V

6 JAZiO Incorporated 5 JAZiO Solution JAZiO has invented a system which –Achieves very high performance –Has edges which can take the whole bit time –Uses differential sensing with very low signal levels –Yet has only 1 pin per data signal

7 JAZiO Incorporated 6 Whats the Secret? A Re-think For each data signal, there is either a change or no-change from the previous bit time Traditional systems are good on no-change but bad on change JAZiO looks for change first and then adjusts if no-change occurs For JAZiO the decision binary is change or no-change rather than high or low voltage

8 JAZiO Incorporated 7 JAZiO Solution Steering Logic Data Output VTR Data Input VTR B A Dual Comparators are used In cases 1 and 6 Comparator A makes a differential comparison In cases 2 and 5 Comparator B makes a differential comparison In the other four cases Data Input does not change Data is driven coincidentally with Voltage/Timing References Data Input VTR One Bit Time Provide alternating Voltage/Timing References switching at the data rate Next Bit Time 8 different combinations of VTR and Data Input

9 JAZiO Incorporated 8 Steering Logic The trick is to know how to select between Comparators A and B and what to do when Data Input does not change

10 JAZiO Incorporated 9 Steering Logic Generate Steering Logic signals (SL and SL ) Use them with Data Output from previous Bit Time to select between Comparators A and B Also use them for data latching SL Receiver Output XOR in out XOR in out Data Input VTR A B Latching System Latched Output

11 JAZiO Incorporated 10 Data Output SL Initialization or Receiver Enable SL VTR Data Input Data Input XOR 55 Small Transistors Per Bit No PLL/DLL Required No die size penalty!!!

12 JAZiO Incorporated 11 The receiver cell is: 22um x 55um (Including routing channels) The pad cell is: 70um x 80um

13 JAZiO Incorporated 12 Time Domain Decision is made in the Time Domain rather voltage domain VTR Data Input First Look for change Determine no- change and switch to Comparator B 0.5V SL Data Output XOR in out XOR in out Data Input VTR A B

14 JAZiO Incorporated 13 A Yes JAZiO Receiver Operation A Rail to Rail SL XOR-B Data Output in out Data Input VTR B XOR-A Rail to Rail Data Input Data Output Initialize VTR Comparator Selected Change? SL CompB CompA XOR-A XOR-B Yes B A No The No-change Cases

15 JAZiO Incorporated 14 The No-Change Case But! The handoff from Comparator A to B is smooth since both of them want to drive Data Output high After the handoff, Comparator B is ready to make the next differential comparison Since Comparator A is selected its high value causes Data Output to remain high Data Output XOR-B in out XOR-A SL Comparator A is selected and as the differential on its inputs disappears the output remains high temporarily However, Comparator B is gaining a differential and its Output becomes a solid high VTR Data Input VTR B A (High) Bit Time But eventually the XORs will switch And Comparator B will be selected

16 JAZiO Incorporated JAZiO Receivers

17 JAZiO Incorporated 16 Data Rate vs Slew Rate Comparison Slower edges Lower switching levels Reduced slew rate Slew Rate (V/nS) Data Rate per Pin (b/S) 10M 100M 1G 10G EDO-33 SDRAM-66 SDRAM-100 DDR RDRAM JAZiO Better Higher Performance at Lower Power with Higher Robustness

18 JAZiO Incorporated 17 Applying JAZiO Technology JAZiO is the physical I/O layer only –JAZiO provides no protocol –Works with any protocol –Like steel belted radial tires that work for Honda Civic, Ferrari Sports Car, or Ford Explorer Easy to use –No die size penalty –No PLL/DLL or special semiconductor technology –Low Power Can be used anywhere that fast switching or low power is useful

19 JAZiO Incorporated 18 JAZiO for DRAM JAZiO Technology can be applied to scaled-up versions of existing protocols like DDR or RDRAM Or new protocols can be developed to match JAZiOs low latency and high bandwidth to reduce pins and increase parallelism

20 JAZiO Incorporated Wide MP Server L3 BSB CONTROLLER FSB CPU 1GHz CPU I/O DRAM 1GHz Data Rate Quad Processor Module 2GHz Interprocessor Communication (Scalable to 4GHz) Quad Processor Module CPU L3 CPU L3 CPU L3 with 2GHz FSB & BSB All scalable to 2x frequencies

21 JAZiO Incorporated 20 Hardware Emulation FPGA Narrow, very high speed JAZiO TM interconnect that allows many FPGAs to appear as a massive logic array

22 JAZiO Incorporated 21 Notebook / Internet Appliance SOCDRAM Power consumed in the memory interface is reduced due to low switching levels of V TT =1.0v and V LOW =0.5v P avg = K vVTTK (Cf+1/R t ) Therefore Power Ratio = (0.5v1)/(0.8v1.8) When compared to existing pseudo differential with VTT=1.8v, v=0.8v, similar load capacitance, operating frequency and termination resistance Small swing and slower transition time reduces EMI, allowing it to be under FCC limits for higher frequency operation JAZiO

23 JAZiO Incorporated 22 How Can JAZiO Be Used? JAZiO is essentially an Open Standard All technology is publicly visible w/o NDA Anyone can see it, study it, simulate it, design it in, build test chips, build prototypes, etc Just dont sell products without licensing it A JAZiO demonstration chip is in design by Micro Magic, Inc – a JAZiO Design Services partner

24 JAZiO Incorporated 23 Conclusion JAZiO uses lower levels and slower edges Achieves high performance, low power, high robustness JAZiO technology is fundamentally different from traditional methods –Time domain rather than voltage domain –Look for change first –Change vs No-change rather than High or Low JAZiO is available to everyone at low cost and applies to any application

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