1. Low Voltage Swing Logic Large Diffusion Connected Network (DCN) produces differential small signals. Extremely high-performance; Expensive reset network, reset cycle, huge load on clock.

2. Current Mode Differential Logic Utilize current mode logic to get stable low- voltage swing. Rs CDL SA S0S0 Xs S1S1 S1’S1’ Shunt transistors and resistors replace reset network. Small transistor count, no reset, small dynamic power, small clock load.

3. CMDL Waveform

4. Current Mode vs. Voltage Mode Time Constant Smaller shunt resistor, faster response. Limited by threshold voltage of sense amplifier. Voltage Mode Current Mode

5. CMDL Design Basic design rules: Any differential input pair must be connected through a shunt resistor or a closed transistor. (No full voltage swing in the circuit) For any differential output pair, only one shunt resistor or closed transistor on the active path. (Differential output signal can be detected) Applicable to extremely high performance low power datapath designs, such as MUX, barrel shifter and carry-skip adder.

6. Preliminary Results Delay (ps) Avg./Peak Power (mW) Delay×Avg. Power LVSCMDLLVSCMDLLVSCMDL 32-bit Mux47.1580.81/4.560.54/0.9038.1531.32 8-bit Shifter3443.20.66/3.200.37/0.4622.4415.98 16-bit Adder70.983.71.08/10.730.16/1.6176.5713.39 DELAY AND POWER COMPARISON BETWEEN CMDL AND LVS CIRCUITS