1. Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. A sketch of a micro four-point probe with integrated CNTs in situ grown from nickel catalyst dots. Figure Legend: From: Wafer scale integration of catalyst dots into nonplanar microsystems J. Micro/Nanolith. MEMS MOEMS. 2007;6(4):043014-043014-9. doi:10.1117/1.2811948

2. Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. The four different methods for integration of nickel catalyst dots into microsystems are compared here in series of sketches of microchip cross sections (not to scale). The abbreviations PR and EBL R stand for photo resist and electron beam lithography resist, respectively. (I) In the direct method, the EBL is performed after finalizing all microprocessing. (II) The in situ mask method starts with the EBL and transfers the pattern into a p-Si layer, which is used as a lift-off mask in the end. (III) The window mask method is a combination of the two preceding methods, where a p-Si layer with open areas (windows) is deposited early on in the process. In the end, the EBL steps are performed inside the windows, with lift-off accomplished for both the EBL resist and the p-Si in KOH. (IV) In the encapsulation method, the EBL and catalyst deposition is done at the beginning. The catalyst pattern is subsequently encapsulated in p-Si, allowing further processing before it is removed in KOH. Figure Legend: From: Wafer scale integration of catalyst dots into nonplanar microsystems J. Micro/Nanolith. MEMS MOEMS. 2007;6(4):043014-043014-9. doi:10.1117/1.2811948

3. Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. The window mask method. (a) After KOH etch of the back side, the chip consists of three layers: silicon dioxide (with TiW leads), p- Si (with window), and aluminum etch mask. A silicon nitride protective layer covers all surfaces (not shown). (b) The silicon nitride layer is removed in RIE. At the same time, the final geometry of the suspended structure is defined by RIE. (c) A selective aluminum etch removes the etch mask. (d) After the EBL step, a lift-off in KOH leaves the structure with nickel dots in the defined locations. Figure Legend: From: Wafer scale integration of catalyst dots into nonplanar microsystems J. Micro/Nanolith. MEMS MOEMS. 2007;6(4):043014-043014-9. doi:10.1117/1.2811948

4. Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. (a) Eight holes in the p-Si layer (see arrows). Note the rounded shape of the underlying silicon dioxide layer. The inset shows a blow up of one of the holes. Arrays of holes in test structures with hole sizes on mask design of (b) 25, (c) 50, (d) 75, and (e) 100nm, respectively. (f) Average hole size and standard deviation on one cantilever from three wafers with etching times 60, 70, and 80s (design diameter: 100nm). (g) Average hole size and standard deviation for various hole size designs in several test arrays as a function of etching time. (h) Total overetch of holes in the test arrays. Figure Legend: From: Wafer scale integration of catalyst dots into nonplanar microsystems J. Micro/Nanolith. MEMS MOEMS. 2007;6(4):043014-043014-9. doi:10.1117/1.2811948

5. Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. (a) Array pattern with 5-, (b) 10-, (c) 20-, and (d) 30-nm nickel. (e) Remaining nickel dots in the test arrays as a function of dot design size and nickel thickness. (f) The nickel dot yield as a function of nickel thickness tends to be largest for thin nickel layers. On average, five cantilevers were inspected for each nickel thickness. All five inspected samples with 5-nm nickel showed a 100% yield. (g) Size of nickel dots in test arrays as a function of nickel thickness and designed dot size. Figure Legend: From: Wafer scale integration of catalyst dots into nonplanar microsystems J. Micro/Nanolith. MEMS MOEMS. 2007;6(4):043014-043014-9. doi:10.1117/1.2811948

6. Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. (a) A cantilever with 5-nm nickel dots. The yield is here seen to be 14 out of 16 designed dots. The inset shows the nickel dots in the test array. (b) Remaining nickel dots in test arrays. (c) Nickel dot size in test arrays. Figure Legend: From: Wafer scale integration of catalyst dots into nonplanar microsystems J. Micro/Nanolith. MEMS MOEMS. 2007;6(4):043014-043014-9. doi:10.1117/1.2811948

7. Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. (a) A SEM image of the structure after RIE etch. The inset shows a close up of the corner. (b) A SEM image after removal of the aluminum etch mask. (c) After KOH lift-off, nickel dots were found on TiW leads. This structure has three out of four dots in place. The inset shows a close up of the nickel dot on one of the TiW leads. (d) On an AFM cantilever structure, the nickel dot is observed in the center (arrow). The inset shows a close up of the cantilever corner, which shows that no nickel is present on the edges. Figure Legend: From: Wafer scale integration of catalyst dots into nonplanar microsystems J. Micro/Nanolith. MEMS MOEMS. 2007;6(4):043014-043014-9. doi:10.1117/1.2811948

8. Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. (a) TiW leads shaped as a micro four-point probe on top of silicon dioxide. The encapsulation method leaves nickel dots on most leads. The inset shows a nickel dot on one of the TiW leads. (b) The nickel dots remain on the silicon dioxide cantilevers (AFM type). Note that the square shape of the dot survives the processing. Figure Legend: From: Wafer scale integration of catalyst dots into nonplanar microsystems J. Micro/Nanolith. MEMS MOEMS. 2007;6(4):043014-043014-9. doi:10.1117/1.2811948