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Ciphering in GSM Mobile Stations Base Station Subsystem Exchange System Network Management Subscriber and terminal equipment databases BSC MSC VLR HLR.

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Presentation on theme: "Ciphering in GSM Mobile Stations Base Station Subsystem Exchange System Network Management Subscriber and terminal equipment databases BSC MSC VLR HLR."— Presentation transcript:

1 Ciphering in GSM Mobile Stations Base Station Subsystem Exchange System Network Management Subscriber and terminal equipment databases BSC MSC VLR HLR EIR AUC OMC BTS A5 Encryption 1

2 Ciphering in GSM A5 CIPHERING SEQUENCE PLAINTEXT SEQUENCE KcKc FRAME NUMBER Sender (Mobile Station or Network) Receiver (Network or Mobile Station) CIPHERTEXT SEQUENCE A5 CIPHERING SEQUENCE KcKc FRAME NUMBER PLAINTEXT SEQUENCE 2

3 A5/1 Overview A5/1 is a stream cipher, which is initialized all over again for every frame sent. Consists of 3 LFSRs of 19, 22, 23 bits length. The 3 registers are clocked in a stop/go fashion using the majority rule. “Cryptography is a mixture of mathematics and muddle, and without the muddle the mathematics can be used against you.” - Ian Cassells, a former Bletchly Park cryptanalyst. 3 Register Number Length In bits Primitive Polynomial Clock-Controlling Bit (LSB is 0) Bits that Are XORed 119 x 19 + x 18 + x 17 + x 16 + x 13 + 1 818,17,16,13 222 x 22 + x 21 + x 20 + 1 1021,20 323 x 23 + x 22 + x 21 + x 20 + x 7 + 1 1022,21,20,7 Parameters of the A5/1 Registers

4 1011110110101101010 1011100100101010111001 10101010011011101100101 clock control 181716 0 21 20 0 0 21 22 20 C3 C2 C1 R2 R1 R3 1 1 0 0 1 011110110101101010 011100100101010111001 0101010011011101100101 111101101011010101 1 1 0 0 1 4

5 A5/1 : Operation All 3 registers are zeroed 64 cycles (without the stop/go clock) : ◦ Each bit of K C (lsb to msb) is XOR'ed in parallel into the lsb's of the registers 22 cycles (without the stop/go clock) : ◦ Each bit of F n (lsb to msb) is XOR'ed in parallel into the lsb's of the registers 100 cycles with the stop/go clock control, discarding the output 228 cycles with the stop/go clock control which produce the output bit sequence. 5


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