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Syed Safi Uddin Qadri BETL/F07/0112 GSM Stream Cipher Algorithm Presented To Sir Adnan Ahmed Siddiqui.

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Presentation on theme: "Syed Safi Uddin Qadri BETL/F07/0112 GSM Stream Cipher Algorithm Presented To Sir Adnan Ahmed Siddiqui."— Presentation transcript:

1 Syed Safi Uddin Qadri BETL/F07/0112 GSM Stream Cipher Algorithm Presented To Sir Adnan Ahmed Siddiqui

2 A5/1 Encryption Algorithm A5/1 A stream cipher providing over-the air communication privacy in GSM A5/1 is used in US and Europe, while A5/2 in other countries. Implemented very efficiently on hardware Variants A5/1 – the strong version A5/2 – the weak version A5/3 GSM Association Security Group and 3GPP design Based on Kasumi algorithm used in 3G mobile systems

3 A5/1 Encryption Mobile StationsBase Station Subsystem Exchange System Network Management Subscriber and terminal equipment databases BSC MSC VLR HLR EIR AUC OMC BTS A5 Encryption

4 A5/1 Logical Implementation A5 K c (64 bit)F n (22 bit) 114 bit XOR Data (114 bit) A5 K c (64 bit)F n (22 bit) 114 bit XOR Ciphertext (114 bit) Data (114 bit) Mobile Station BTS Real A5 output is 228 bit for both directions

5 A5/1 Key Generation The same key Kc is used to encrypt and decrypt the conversation How is the Kc generated? Ki – root encryption key Unique for each subscriber A3 – authenticate the user to the mobile operator A8 – Generate Kc

6 LFSR Structure A5/1 based on Linear Feedback Shift Registers: LFSRs Purpose - to produce pseudo random bit sequence Consists of two parts : shift register – bit sequence feedback function Tap Sequence : bits that are input to the feedback function b0b0b0b0 b1b1b1b1 b2b2b2b2 b3b3b3b b n-1 bnbnbnbn Feedback Function : XOR output new value

7 LFSR Example Example : x 11 +x 5 +x 3 +1 corresponds to LFSR of length 12 b0b0b0b0 b1b1 b2b2 b3b3b3b3 b4b4 b5b5b5b5 b6b6 b7b7 b8b8 b9b9 b 10 b 11

8 A5/1 LFSRs Consists of 3 LFSRs of different lengths 19 bits x 18 + x 17 + x 16 + x clock bit 8 tapped bits: 13, 16, 17, bits x 21 + x clock bit 10 tapped bits 20, bits x 22 + x 21 + x 20 + x clock bit 10 tapped bits 7, 20, 21, 22

9 A5/1 Description Clocking Clocking mechanism is based on majority function If the clocking bit agrees with the majority bit Probability of each register to be clocked is 3/4

10 A5/1 Description Algorithm (initial state) Zero all registers For each bit of the Kc: Rj[0]=Rj[0]+Kc[i], j=(1,2,3) Clock the registers ignoring the regular clocking mechanism For each bit of the Fn: Rj[0]=Rj[0]+Fn[i], j=(1,2,3) Clock the registers ignoring the regular clocking mechanism Clock the registers with the normal clocking mechanism for 100 rounds and discard the output

11 Clocking Mechanism C3 C2 C1 R2 R1 R A5/1 Description

12 Algorithm (cipher text generation) Clock the cipher 114 times using the normal stop/go fashion Produce 114 bits (keystream) by XOR-ing the MSBs of the three registers This keystream will be used to encrypt the communication between operator and mobile station XOR the keystream with the initial message to produce the ciphertext Do the same for the conversation between mobile station and operator

13 Clocking Mechanism C3 C2 C1 R2 R1 R A5/1 Working Example

14 THANK YOU!


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